AD9540 Analog Devices, AD9540 Datasheet - Page 8

• Manufacturer Part Number: AD9540
• Description: 655 MHZ Low Jitter Clock Generator
• Manufacturer: Analog Devices

AD9540
Parameter
1
2
3
4
5
6
7
8
The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock,
not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated.
Driving the PLLREF input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz.
The charge pump output compliance range is functionally 0.2 V to (CPVDD − 0.2 V). The value listed here is the compliance range for 5% matching.
The input impedance of the CLK1 input is 1500 Ω. However, to provide matching on the clock line, an external 50 Ω load is used.
Measured as peak-to-peak between DAC outputs.
For a 4.02 kΩ resistor from DRV_RSET to GND.
IBIS models for the digital I/O pins available upon request.
Assumes a 1 mA load.
51.84 MHz F
105 MHz Analog Out
155.52 MHz Analog Out
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
> 1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
OUT
Min
Rev. 0 | Page 8 of 32
Typ
110
121
135
142
148
153
105
115
126
132
140
145
100
112
123
131
138
144
Max
Unit
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dBc/Hz
dBc/Hz
dBc/Hz
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dBc/Hz
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Test Conditions/Comments