LM2635 National Semiconductor, LM2635 Datasheet - Page 2

• Manufacturer Part Number: LM2635
• Description: 5-Bit Programmable Synchronous Buck Regulator Controller
• Manufacturer: National Semiconductor

www.national.com
Connection Diagram
Pin Descriptions
LSGATE (Pin 1): Gate drive for the low-side N-channel
MOSFET. This signal is interlocked with HSGATE (Pin 20) to
avoid a shoot-through problem.
BOOTV (Pin 2): Power supply for high-side N-channel
MOSFET gate drive. The voltage should be at least one gate
threshold above the converter input voltage to properly oper-
ate the high-side N-FET.
PGND (Pin 3): Ground for high current circuitry. It should be
connected to system ground.
SGND (Pin 4): Ground for signal level circuitry. It should be
connected to system ground.
V
SENSE (Pin 6): Converter output voltage sensing. It pro-
vides input for power good, fast dual comparator control
loop, and over-voltage protection circuitry. It is recom-
mended that a 0.1 µF capacitor be connected between this
pin and ground to avoid potential noise problems.
IMAX (Pin 7): Current limit threshold setting. It sinks a fixed
180 µA current. By connecting a resistor between the high
side MOSFET drain and this pin, a fixed voltage drop can be
built across the resistor. This voltage drop is compared with
the V
current condition has occurred.
IFB (Pin 8): High-side N-MOSFET source voltage sensing.
This pin is one V
lower than that of IMAX pin during the time the high-side FET
is on, it means V
the IMAX resistor, which can be interpreted as an over-
current condition.
V
mainly for use by other power supplies on the motherboard
which need a reference.
EA_OUT (Pin 10): Output of the error amplifier. The voltage
level on this pin is compared with an internally generated
ramp signal to determine the duty cycle. This pin is neces-
sary for compensating the primary control loop.
FB (Pin 11): Inverting input of the error amplifier. A pin nec-
essary for compensating the control loop.
FREQ_ADJ (Pin 12): Switching frequency adjustment.
Switching frequency can be adjusted by changing the
grounding resistance on this pin.
CC
REF
(Pin 5): Power supply for the controller.
DS
(Pin 9): Bandgap reference voltage. This voltage is
of the high-side N-MOSFET to determine if an over-
See NS Package Number M20B
DS
Order Number LM2635M
DS
below drain voltage. When this voltage is
is higher than the preset voltage across
Plastic SO-20
TOP VIEW
DS100119-3
2
PWRGD (Pin 13): Power Good. There are two windows
around the DAC output voltage that are associated with
PWRGD pin, the
PWRGD is initially high (open drain state) and output voltage
travels out of
pedance to ground). If PWRGD is initially low and output
voltage travels into the
the window for at least 10 ms, PWRGD goes to high. A
PWRGD high means the output voltage is at least within the
±
voltage is definitely outside the
VID4:0 (Pins 14, 15, 16, 17, 18): Voltage Identification
Code. The five pins accept an open-ground pattern 5-bit bi-
nary code from outside the chip (typically from the CPU) for
generating the desired output voltage. Each VID pin is inter-
nally pulled up to V
shows the code table.
OUTEN (Pin 19): Output Enable. The output voltage is dis-
abled when this pin is pulled low. It is internally pulled up to
V
HSGATE (Pin 20): Gate drive for the high-side N-channel
MOSFET. This signal is interlocked with LSGATE (Pin 1) to
avoid a shoot-through problem.
V
CC
10% window whereas a PWRGD low indicates the output
ID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
via a 90 µA current source.
V
ID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
TABLE 1. VID Code and DAC Output
V
±
ID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
10% window, PWRGD goes to low (low im-
±
CC
10% window and the
V
ID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
via a 90 µA current source. Table 1
±
8% window and has stayed within
V
ID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
±
8% window.
Rated Output
Voltage (V)
(shutdown)
(#) (1.30)
(#) (1.35)
(#) (1.40)
(#) (1.45)
(#) (1.50)
(#) (1.55)
(#) (1.60)
(#) (1.65)
(#) (1.70)
(#) (1.75)
1.80
1.85
1.90
1.95
2.00
2.05
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
±
8% window. If