LM2636 National Semiconductor, LM2636 Datasheet - Page 7

• Manufacturer Part Number: LM2636
• Description: 5-Bit Programmable Synchronous Buck Regulator Controller
• Manufacturer: National Semiconductor

Applications Information
OVERVIEW
The LM2636 is a high speed synchronous PWM buck regu-
lator controller designed for VRM vendors or motherboard
manufacturers who need to build on-board power supplies
for Cyrix MII, Pentium II or Deschutes microprocessors. It
has a built-in 5-bit DAC to decode the 5-bit word provided by
the CPU and supply the corresponding voltage. It also has
the power good (PWRGD) and output enable (OUTEN) func-
tions required by the VRM specification. It employs a voltage
mode control scheme plus two fast responding comparators
to quickly respond to large load transients. It has two fast
FET drivers to drive the high-side and low-side NMOS
switches of a synchronous buck regulator. The PWM fre-
quency is adjustable from 50 kHz to 1 MHz through an exter-
nal resistor. Over-voltage protection is achieved by shutting
off the high-side driver and turning on the low-side driver
100% of the time. Current limiting is implemented by sensing
V
present switching cycle when an over current condition is de-
tected. Soft start functionality is realized through an internal
digital counter and an internal DAC.
THEORY OF OPERATION
Start Up
When V
and the VID code is valid, the soft start circuitry starts to
work. The duration of the soft start is determined by an inter-
nal digital counter and the switching frequency. During soft
start, the output of the error amplifier is allowed to increase
gradually. When the counter has counted 2,048 clock cycles,
the soft start session ends and the output voltage level of the
error amplifier is released and allowed to go to a value that is
determined by the feedback loop. PWRGD pin is forced low
during soft start and is turned over to output voltage monitor-
ing circuitry after that. Before V
logic is in a power on reset state and the two FET drivers are
disabled.
During normal operation, if V
the internal circuitry will go into power on reset again. The
hysteresis helps decrease the noise sensitivity on the V
pin. After soft starts ends and during normal operation, if the
converter output voltage exceeds 115% of the DAC output
voltage, the LM2636 will lock into over voltage protection
mode. The high side drive will be disabled, and the low side
drive will be high. There are two ways to clear the mode. One
is to cycle V
OUTEN level. After the over voltage protection mode is
cleared, the LM2636 will enter the soft start session and start
over.
Normal Operation
During the normal operation mode, the LM2636 regulates
the converter output voltage by adjusting the duty ratio. The
output voltage is determined by the 5-bit VID code set by the
user/load.
The PWM frequency is set by the external resistor between
FREQ_ADJ pin and ground. The resistance needed for a de-
sired switching frequency is:
DS
of the high-side NMOS switch and shutting it off for the
CC
voltage exceeds 4.2V, OUTEN pin is a logic high
CC
voltage once. The other is to toggle the
CC
CC
voltage drops below 3.8V,
reaches 4.2V, all internal
CC
7
For example, if the desired switching frequency is 300 kHz,
the resistance should be around 84 k .
The minimum allowable PWM frequency is 5 kHz.
MOSFET Gate Drive
The LM2636 has two gate drives that are suitable for driving
external N-MOSFETs in a synchronous buck topology. The
power for the two FET drivers is supplied by the BOOTV pin.
This BOOTV voltage needs to be at least one V
than the converter input voltage for the high side FET to be
fully turned on. The voltage can be either supplied from
a separate source other than the input voltage or can be
generated locally by utilizing a charge pump structure. In a
typical desktop microprocessor application, if 5V is chosen
to be the input voltage, then 12V can be used for the
BOOTV. If 12V is not available, a simple charge pump cir-
cuitry consisting of a diode and a small capacitor can be
used, as shown in Figure 3 .
FIGURE 3. BOOTV Voltage Supplied by a Charge Pump
When the low side FET is on, the charge pump capacitor is
charged to near the input voltage through the diode. When
low side FET is turned off, the high side FET driver is en-
abled, and the charge pump capacitor starts to charge the
high side FET gate until it is fully on. By this time the high
side FET source node will fly to close to input voltage level
and the upper node of the capacitor will also fly to one input
voltage higher than the input voltage, enabling the high side
FET driver to continue working.
For a BOOTV of 12V, the initial gate charging current is typi-
cally 2A, and the initial gate discharging current is typically
6A, good for high speed switching.
The LM2636 gate drives are of BiCMOS design. Unlike
some other bipolar VRM control ICs, the gate drive has rail-
to-rail swing that ensures no spurious turn-on due to capaci-
tive coupling.
Another feature of the FET gate drives is the adaptive non-
overlapping mechanism. A gate driver is not turned on until
the other is fully off. The dead time in between is typically 20
ns. This avoids the potential shoot-through problem and
helps improve efficiency.
Load Transient Response
In a typical modern MPU application such as the Pentium II
core voltage power supply, load transient response is a criti-
cal issue. The LM2636 utilizes the conventional voltage
feedback technology as the primary feedback control
method. When the load transient happens, the error in the
output voltage level is fed to the error amplifier. The output of
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