AD9834 Analog Devices, AD9834 Datasheet - Page 10

• Manufacturer Part Number: AD9834
• Description: +2.5V to +5.5V, 50MHz, Low Power (25mW) Complete DDS With on Board Comparator in 20-pin Tssop Package
• Manufacturer: Analog Devices

FUNCTIONAL DESCRIPTION
Serial Interface
The AD9834 has a standard 3-wire serial interface, which
is compatible with SPI, QSPI, MICROWIRE and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing dia-
gram for this operation is given in Figure 4.
The FSYNC input is a level triggered input that acts as a
frame synchronisation and chip enable. Data can only be
transferred into the device when FSYNC is low. To start
the serial data transfer, FSYNC should be taken low, ob-
serving the minimum FSYNC to SCLK falling edge setup
time, t
into the device's input shift register on the falling edges of
SCLK for 16 clock pulses. FSYNC may be taken high
after the sixteenth falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time,
t
16 SCLK pulses, and then brought high at the end of the
data transfer. In this way, a continuous stream of 16 bit
words can be loaded while FSYNC is held low, FSYNC
only going high after the 16th SCLK falling edge of the
last word loaded.
The SCLK can be continuous or, alternatively, the SCLK
can idle high or low between write operations.
Powering up the AD9834
The flow chart in Figure 7 shows the operating routine for
the AD9834. When the AD9834 is powered up, the part
should be reset. This will reset appropriate internal regis-
ters to zero to provide an analog output of midscale. To
avoid spurious DAC outputs while the AD9834 is being
initialized, the RESET bit/pin should be set to 1 until the
part is ready to begin generating an output. RESET does
not reset the phase, frequency or control registers. These
registers will contain invalid data and, therefore, should be
set to a known value by the user. The RESET bit/pin
should then be set to 0 to begin generating an output. A
8
AD9834
. Alternatively, FSYNC can be kept low for a multiple of
7
. After FSYNC goes low, serial data will be shifted
SLEEP1
SLEEP12
MODE + OPBITEN
DIV2
SIGNPIB
OPBITEN
Accumulator
(28 Bit)
Phase
PRELIMINARY TECHNICAL DATA
Div
by 2
ROM
SIN
Figure 6. Function of Control Bits
MUX
0
1
MUX
0
1
MUX
1
0
–10–
COMPARATOR
(Low Power)
10 - Bit DAC
signal will appear at the DAC output 7 MCLK cycles after
RESET is set to 0.
Latency
Associated with each operation is a latency. When the pins
FSELECT and PSELECT change value there is a pipe-
line delay before control is transfered to the selected
register. When the timing specifications t11 and t11A are
met (see figure 3) FSELECT and PSELECT have laten-
cies of 7 MCLK cycles. When the timing specifications
t11 and t11A are not met, the latency is increased by one
MCLK cycle.
Similarly there is a latency associated with each asynchro-
nous write operation. If a selected frequency/phase register
is loaded with a new word there is a delay of 7 to 8 MCLK
cycles before the analog output will change. (There is an
uncertainty of one MCLK cycle as it depends on the posi-
tion of the MCLK rising edge when the data is loaded into
the destination register.)
The negative transition of the RESET and SLEEP func-
tions are sampled on the internal falling edge of MCLK,
therefore also have a latency associated with them.
The Control Register
The AD9834 contains a 16-bit control register which sets
up the AD9834 as the user wishes to operate it. All control
bits, except MODE, are sampled on the internal negative
edge of MCLK.
Table 2, on the following page, describes the individual
bits of the control register. The different functions and the
various output options from the AD9834 are described in
more detail in the section following Table 2.
To inform the AD9834 that you wish to alter the contents
of the Control register, D15 and D14 must be set to '0' as
shown below.
D15
0
D14
0
AD9834
D13
DIGITAL
OUTPUT
(enable)
Table 1. Control Register
CONTROL BITS
IOUT
IOUTB
VIN
SIGN BIT OUT
REV PrL
D0