MAX1036 Maxim, MAX1036 Datasheet - Page 9

• Manufacturer Part Number: MAX1036
• Description: 2.7V to 5.5V / Low-Power / 4-/12-Channel 2-Wire Serial 8-Bit ADCs
• Manufacturer: Maxim

Figure 1. I
of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or series of conversions are
then internally clocked (eight clock cycles per conver-
sion) and the MAX1036–MAX1039 hold SCL low. When
operating in external clock mode, the T/H circuitry
enters track mode on the seventh falling edge of a valid
slave address byte. Hold mode is then entered on the
falling edge of the eighth clock cycle. The conversion is
performed during the next eight clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
between conversions. The acquisition time (t
minimum time needed for the signal to be acquired. It
is calculated by:
where R
R
IN
= 2.5kΩ, and C
A. F/S-MODE I
B. HS-MODE I
SDA
SDA
SCL
SCL
SOURCE
2
t
S
S
C Serial Interface Timing
ACQ
t
t
HD.STA
HD.STA
2
2
C SERIAL INTERFACE TIMING
C SERIAL INTERFACE TIMING
≥ 6.25
is the analog input source impedance,
t
t
_______________________________________________________________________________________
LOW
LOW
IN
✕
2.7V to 5.5V, Low-Power, 4-/12-Channel
= 18pF. t
t
t
RCL
(R
R
t
SU.DAT
t
SU.DAT
SOURCE
t
t
HIGH
HIGH
ACQ
t
FCL
t
F
+ R
is 1/f
IN
t
t
HD.DAT
HD.DAT
)
SCL
✕
C
ACQ
IN
for external
) is the
HS-MODE
t
t
SU.STA
SU.STA
2-Wire Serial 8-Bit ADCs
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select R
allow 625ns for t
for clock frequency variations.
Figure 2. Load Circuit
Sr
Sr
t
HD.STA
t
HD.STA
SDA
A
A
ACQ
in internal clock mode to account
V
t
DD
RCL1
t
t
SU.STO
SU.STO
I
I
OL
OH
t
RDA
= 3mA
= 0mA
400pF
t
V
R
OUT
P
t
t
BUF
BUF
F/S-MODE
t
F
SOURCE
S
S
t
t
FDA
9
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