MAX1124 Maxim Integrated Products, MAX1124 Datasheet - Page 12

• Manufacturer Part Number: MAX1124
• Description: 250Msps Analog-to-Digital Converter
• Manufacturer: Maxim Integrated Products

with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degrada-
tion in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2V
and are usually driven in AC-coupled configuration.
See the Differential, AC-Coupled Clock Input in the
Applications Information section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
The MAX1124 also features an internal clock manage-
ment circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of >20MHz to work appropriately and accord-
ing to data sheet specifications.
The MAX1124 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Table 1. MAX1124 Digital Output Coding
12
VOLTAGE LEVEL
> V
< V
V
______________________________________________________________________________________
V
INP ANALOG
CM
CM
CM
CM
+ 0.3125V
V
- 0.3125V
+ 0.3125V
- 0.3125V
CM
Clock Outputs (DCLKP, DCLKN)
VOLTAGE LEVEL
> V
< V
V
V
INN ANALOG
CM
CM
CM
CM
+ 0.3125V
- 0.3125V
V
+ 0.3125V
- 0.3125V
CM
P-P
to 1.0V
OUT-OF-RANGE
ORP (ORN)
1 (0)
0 (1)
0 (1)
0 (1)
1 (0)
P-P
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See
The MAX1124 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that only operate with update rates one-half of the con-
verter’s sampling rate. Connecting CLKDIV to OV
allows data to be updated at the speed of the ADC input
clock.
Figure
input and output, analog input, sampling event, and
data output. The MAX1124 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of nine clock cycles.
(exceeds negative full scale,
(exceeds positive full scale,
DIGITAL OUTPUT CODE
Figure
(represents negative full
(represents positive full
(represents midscale)
4 depicts the relationship between the clock
10 0000 0000 or
11 1111 1111
11 1111 1111
01 1111 1111
00 0000 0000
00 0000 0000
Divide-by-2 Clock Control (CLKDIV)
4 for timing details.
BINARY
(D9–D0)
OR set)
OR set)
scale)
scale)
System Timing Requirements
(exceeds negative full scale,
(exceeds positive full scale,
DIGITAL OUTPUT CODE
(represents negative full
TWO’S COMPLEMENT
(represents positive full
(represents midscale)
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00 0000 0000 or
01 1111 1111
01 1111 1111
11 1111 1111
10 0000 0000
10 0000 0000
(D9–D0)
OR set)
OR set)
scale)
scale)
CC