MAX1182 Maxim Integrated Products, MAX1182 Datasheet - Page 5

• Manufacturer Part Number: MAX1182
• Description: Low-Power ADC
• Manufacturer: Maxim Integrated Products

ELECTRICAL CHARACTERISTICS (continued)
(V
10kΩ resistor, V
T
Note 1: Equivalent dynamic performance is obtainable over full OV
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
Note 5: Digital outputs settle to V
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
A
DD
= T
= 3V, OV
Dual 10-Bit, 65Msps, 3V, Low-Power ADC with
MIN
input voltage range.
6dB or better, if referenced to the two-tone envelope.
to T
PARAMETER
MAX
DD
IN
= 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
, unless otherwise noted. Typical values are at T
= 2Vp-p (differential w.r.t. COM), C
_______________________________________________________________________________________
Internal Reference and Parallel Outputs
IH
, V
SYMBOL
t
t
DISABLE
IL
ENABLE
PDISS
OV
I
t
PSRR
OVDD
WAKE
I
V
t
t
. Parameter guaranteed by design.
VDD
t
DO
CH
CL
DD
DD
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, C
f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Offset
Gain
Figure 3 (Note 5)
Figure 4
Figure 4
Figure 3, clock period: 15.4ns
Figure 3, clock period: 15.4ns
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
f
f
f
INA or B
INA or B
INA or B
INA or B
= 20MHz at -0.5dBFS
= 20MHz at -0.5dBFS
= 20MHz at -0.5dBFS
= 20MHz at -0.5dBFS
L
= 10pF at digital outputs (Note 1), f
INA or B
INA or B
L
= 15pF,
CONDITIONS
A
DD
= +25°C.) (Note 2)
= 20MHz at -0.5dBFS
= 20MHz at -0.5dBFS
range with reduced C
DD
DD
DD
L
.
MIN
2.7
1.7
CLK
= 65MHz (50% duty cycle),
7.7 ± 1.5
7.7 ± 1.5
TYP
±0.2
±0.1
0.42
0.02
0.25
100
195
3.0
2.5
2.8
8.4
1.5
1.5
-70
65
11
10
1
2
3
5
MAX
±0.2
240
3.6
3.6
80
15
10
45
8
d eg r ees
UNITS
mV/V
%/V
mW
mA
mA
µW
µA
µA
dB
dB
ns
ns
ns
ns
ns
µs
V
V
5