MAX1186 Maxim Integrated Products, MAX1186 Datasheet - Page 5

• Manufacturer Part Number: MAX1186
• Description: Low-Power ADC
• Manufacturer: Maxim Integrated Products

ELECTRICAL CHARACTERISTICS (continued)
(V
10kΩ resistor, V
T
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
Note 3: Digital outputs settle to V
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OV
A
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
Internal Reference and Multiplexed Parallel Outputs
DD
= T
= 3V, OV
MIN
input voltage range.
6dB or better, if referenced to the two-tone envelope.
to T
PARAMETER
MAX
DD
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
, unless otherwise noted. Typical values are at T
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
IN
_______________________________________________________________________________________
= 2V
P-P
IH
(differential w.r.t. COM), C
and V
SYMBOL
t
t
DISABLE
ENABLE
PDISS
I
t
OV
PSRR
t
OVDD
t
t
WAKE
I
V
DA/B
DOA
DOB
VDD
t
t
CH
CL
DD
DD
IL
. Parameter guaranteed by design.
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, C
-0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OV
Operating, f
Sleep mode
Shutdown, clock idle, PD = OE = OV
Offset
Gain
Figure 3 (Note 3)
Figure 3 (Note 3)
Figure 4
Figure 4
Figure 3, clock period: 25ns
Figure 3, clock period: 25ns
Wake-up from sleep mode (Note 4)
Wake-up from shutdown (Note 4)
f
f
f
INA or B
INA or B
INA or B
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
INA or B
INA or B
L
= 15pF, f
CONDITIONS
A
L
DD
= +25°C.)
= 20MHz at -0.5dB FS
= 20MHz at -0.5dB FS
= 10pF at digital outputs (Note 5), f
range with reduced C
INA or B
= 20MHz at
DD
DD
DD
L
.
MIN
2.7
1.7
12.5 ±3.8
12.5 ±3.8
TYP
±0.2
±0.1
0.41
0.02
0.25
100
105
3.0
2.5
-70
2.8
8.4
1.5
1.5
35
10
1
4
2
3
5
5
6
CLK
MAX
±0.2
150
3.6
3.6
50
15
10
45
8
8
= 40MHz,
d eg r ees
UNITS
mV/V
mW
%/V
mA
mA
µW
dB
dB
µA
µA
ns
ns
ns
ns
ns
ns
ns
µs
V
V
5