MAX1245 Maxim, MAX1245 Datasheet - Page 13

• Manufacturer Part Number: MAX1245
• Description: +2.375V / Low-Power / 8-Channel / Serial 12-Bit ADC
• Manufacturer: Maxim

selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provid-
ed that the minimum acquisition time, t
above 2.0µs.
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
SSTRB
SCLK
DOUT
CS
SSTRB
A/D STATE
DOUT
SCLK
DIN
CS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
START
______________________________________________________________________________________
1
PD0 CLOCK IN
SEL2 SEL1 SEL0 UNI/
2
3
IDLE
t
CSH
4
BIP
5
(SCLK = 1.5MHz)
SGL/
DIF
ACQUISITION
6
Data Framing
+2.375V, Low-Power, 8-Channel,
2.0µs
PD1 PD0
t
SSTRB
7
ACQ
8
, is kept
(SHDN = FLOAT)
CONVERSION
7.5µs MAX
t
t
CONV
CONV
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated,
and a new one is started.
9
MSB B10
B11
IDLE
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
10
11
B9
12
Serial 12-Bit ADC
t
SCK
18
B2
19
B1
20
LSB
OR
B0
21
t
CSS
FILLED WITH
ZEROS
22
23
DD
24
t
DO
is applied.
13