MAX+PLUSII Altera Corporation, MAX+PLUSII Datasheet - Page 3

• Manufacturer Part Number: MAX+PLUSII
• Description: Programmable Logic Development System & Software
• Manufacturer: Altera Corporation

MAX+PLUS II
Design Process
Figure 1. MAX+PLUS II Design Environment
Altera Corporation
High-Level
Design
Entry
Standard
EDA
Design
Entry
abcde
ab
abc
edif
c
d
Design Entry
Text Design Entry
(AHDL, VHDL, & Verilog HDL)
MegaCore Functions
LPM Functions
AMPP Megafunctions
Cadence
Mentor Graphics
Synopsys
Viewlogic
Synplicity
Exemplar Logic
Others
Graphic
Design Entry
Waveform
Design Entry
Hierarchical
Design Entry
Floorplan
Editing
MAX+PLUS II Programmable Logic Development System & Software Data Sheet
The MAX+PLUS II design process, shown in
phases: design entry, design compilation, design verification, and device
programming.
Design Entry
The MAX+PLUS II software can integrate multiple design files—
generated with MAX+PLUS II design entry tools or with a variety of other
industry-standard EDA design entry tools—into a single design
hierarchy. The extensive integration between MAX+PLUS II applications
allows information to flow freely to and from each application. For
example, any errors identified during compilation, simulation, and
timing analysis can be automatically located and highlighted in the
original design file or in the Floorplan Editor. If a design (called a
“project” in the MAX+PLUS II software) consists of two or more levels of
hierarchy, the user can navigate from one design file directly to any other
design file in the hierarchy, regardless of whether it is graphic-, text-, or
waveform-based.
Design Compilation
MAX+PLUS II Compiler
Timing-
Driven
Compilation
OpenCore
Evaluation
Design-Rule
Checking
Logic
Synthesis &
Fitting
Multi-Device
Partitioning
Automatic
Error
Location
Standard
EDA
Verification
Verification & Programming
Figure
edif
1, consists of four
OpenCore
Evaluation
Cadence
Mentor Graphics
Synopsys
Viewlogic
Others
Timing
Simulation
Functional
Simulation
Multi-Device
Simulation
Timing
Analysis
Device
Programming
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