MAX1270ACAI Maxim, MAX1270ACAI Datasheet - Page 13

• Manufacturer Part Number: MAX1270ACAI
• Description: Multirange / +5V / 8-Channel / Serial 12-Bit ADCs
• Manufacturer: Maxim

Figure 9. Internal Clock Mode, 20 SCLK/Conversion Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
conversion in progress. Figure 10 shows the SSTRB
timing in internal clock mode.
Internal clock mode conversions can be completed
with 13 external clocks per conversion but require a
waiting period of 15µs for the conversion to be com-
pleted (Figure 11).
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clock cycles; 16 clock cycles per
conversion, as shown in Figure 12, will typically be the
most convenient way for a microcontroller to drive the
MAX1270/MAX1271.
SSTRB
SCLK
CS
• • •
• • •
• • •
SSTRB
DOUT
A/D STATE
SCLK
DIN
CS
HIGH-Z
____________________________________________________________________________________
START SEL2 SEL1 SEL0 RNG
MSB
1
SCLK #8
t
CSH
BIP
PD1
ACQUISITION
2 EXT SCLK
+4 INT CLK
t
SSTRB
PD0
LSB
8
16 INT CLK
CONVERSION
Multirange, +5V, 8-Channel,
12 INT CLK
HIGH-Z
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
MSB
The MAX1270/MAX1271 power up in normal operation
(all internal circuitry active) and internal clock mode,
waiting for a start bit. The contents of the output data
register are cleared at power-up.
The MAX1270/MAX1271 operate with either an internal
or external reference. An external reference is connect-
ed to either REF or REFADJ (Figure 13). The REFADJ
internal buffer gain is trimmed to 1.638V to provide
4.096V at REF from a 2.5V reference.
D11 D10
9
10
D1
19
Serial 12-Bit ADCs
LSB
D0
20
Applications Information
Internal or External Reference
t
SCK
FILLED WITH ZEROS
t
CSS
Power-On Reset
HIGH-Z
7-181