MAX1333 Maxim Integrated Products, MAX1333 Datasheet - Page 21

• Manufacturer Part Number: MAX1333
• Description: (MAX1332 / MAX1333) True-Differential 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

Figure 17. DSP Interface—Continuous Conversion
Figure 18. DSP Interface—Single Conversion—Continuous/Burst Clock
enabled when using the buffered serial port to read the
data without µC intervention. Connect DV
TMS320C54_ supply voltage.
The MAX1332/MAX1333 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the transmit clock (CLKX) generated
internally to drive SCLK. A pullup resistor is required on
the CNVST signal to keep it high when DX goes high
impedance and write (0001)h to the data transmit regis-
ter (DXR) continuously for continuous conversions. The
power-down modes can be entered by writing (00FF)h
to the DXR (see Figures 17 and 18).
The MAX1332/MAX1333 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices.
Figure 19 shows the direct connection of the
MAX1332/MAX1333 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to inter-
face with the MAX1332/MAX1333. For continuous con-
versions, idle CNVST low and pulse it high for one
clock cycle during the LSB of the previous transmitted
word. Configure the ADSP21_ _ _ STCTL and SRCTL
registers for early framing (LAFR = 0) and for an active-
CNVST
DOUT
SCLK
CNVST
DOUT
SCLK
D0
DSP Interface to the ADSP21_ _ _
1
0
0
______________________________________________________________________________________
0
1
0
0
3Msps/2Msps, 5V/3V, 2-Channel, True-
0
D11
0
D10
D11
D9
D10
D8
DD
D7
D9
to the
D6
D8
D5
8
Differential 12-Bit ADCs
D7
high frame (LTFS = 0, LRFS = 0) signal. In this mode,
the data-independent frame-sync bit (DITFS = 1) can
be selected to eliminate the need for writing to the
transmit data register more than once. For single con-
versions, idle CNVST high and pulse it low for the entire
conversion. Configure the ADSP21_ _ _ STCTL and
SRCTL registers for late framing (LAFR = 1) and for an
active-low frame (LTFS = 1, LRFS = 1) signal. This is
also the best way to enter the power-down modes by
setting the word length to 8 bits (SLEN = 0111).
Connect the DV
age (see Figures 17 and 18).
For best performance, use PC boards. Wire-wrap
boards must not be used. Board layout must ensure
that digital and analog signal lines are separated from
each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines
underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish an analog ground point at
AGND and a digital ground point at DGND. Connect all
other analog grounds to the analog ground point.
D4
D6
D3
D5
D2
Layout, Grounding, and Bypassing
D4
D1
DD
D3
pin to the ADSP21_ _ _ supply volt-
D0
D2
0
D1
D0
16
0
1
0
1
0
0
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