MAX148 Maxim, MAX148 Datasheet - Page 7

• Manufacturer Part Number: MAX148
• Description: +2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCs
• Manufacturer: Maxim

Figure 1. Load Circuits for Enable Time
______________________________________________________________Pin Description
DOUT
PIN
a) High-Z to V
1–8
10
11
12
13
14
15
16
17
18
19
20
9
6k
OH
DGND
CH0–CH7
REFADJ
and V
SSTRB
NAME
AGND
DGND
SHDN
DOUT
SCLK
VREF
COM
V
DIN
CS
DD
OL
_______________________________________________________________________________________
to V
+2.7V to +5.25V, Low-Power, 8-Channel,
OH
C
50pF
LOAD
Sampling Analog Inputs
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are
fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.
Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
Analog Ground
Digital Ground
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
Positive Supply Voltage
b) High-Z to V
DOUT
DD
V
DD
OL
.
and V
6k
C
DGND
50pF
LOAD
OH
to V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
DOUT
6k
Serial 10-Bit ADCs
a) V
OH
DGND
to High-Z
C
50pF
LOAD
DOUT
b) V
OL
V
to High-Z
DD
6k
C
50pF
DGND
LOAD
DD
.
7