MAX1492 Maxim, MAX1492 Datasheet - Page 5

• Manufacturer Part Number: MAX1492
• Description: 3.5- and 4.5-Digit / Single-Chip ADCs with LCD Drivers
• Manufacturer: Maxim

TIMING CHARACTERISTICS (Notes 10, 11 and Figure 13)
(AV
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
Note 2: Offset calibrated. See the
Note 3: Offset nulled.
Note 4: Drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: V
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
Note 8: CLK and SCLK are idle.
Note 9: Power-supply currents are measured with all digital inputs at either GND or DV
Note 10: All input signals are specified with t
Note 11: See the serial-interface timing diagrams.
PARAMETER
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Fall to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DD
= DV
and offset error.
AIN+ and REF+ only.
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
DV
AIN+
DD
DD
= 2.7V to +5.25V, GND = 0, T
, unless otherwise noted.
or V
AIN-
_______________________________________________________________________________________
= -2.2V to +2.2V. V
3.5- and 4.5-Digit, Single-Chip ADCs
OFFSET_CAL1 and OFFSET_CAL2 sections in the On-Chip Registers section.
SYMBOL
f
t
SCLK
t
t
t
t
CSH
t
t
CSS
t
t
DO
CH
DH
CL
DS
TR
DV
REF+
A
RISE
= T
MIN
or V
C
C
C
= t
LOAD
LOAD
LOAD
FALL
to T
REF-
MAX
= 50pF (Figures 18, 19)
= 50pF (Figures 18, 19)
= 50pF (Figures 18, 19)
= 5ns (10% to 90% of DV
= -2.2V to +2.2V. All input structures are identical. Production tested on
, unless otherwise noted.)
CONDITIONS
DD
DD
) and are timed from a voltage level of 50% of
with LCD Drivers
and with the device in internal clock mode.
MIN
100
100
50
50
0
0
0
TYP
MAX
120
120
120
4.2
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
5