MAX15025 Maxim Integrated Products, MAX15025 Datasheet - Page 11

• Manufacturer Part Number: MAX15025
• Description: (MAX15024 / MAX15025) High Sink/Source Current Gate Drivers
• Manufacturer: Maxim Integrated Products

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Figure 1. Timing Diagram
Power dissipation of the MAX15024/MAX15025 con-
sists of three components: the quiescent current,
capacitive charge and discharge of internal nodes, and
the output current (either capacitive or resistive load).
The sum of these components must be kept below the
maximum power-dissipation limit. The quiescent cur-
rent is 700µA typ. The current required to charge and
discharge the internal nodes is frequency dependent
(see the Typical Operating Characteristics ). The
MAX15024/MAX15025 power dissipation when driving
a ground-referenced resistive load is:
where D is the fraction of the period the MAX15024/
MAX15025s’ output pulls high, R
mum on-resistance of the device with the output high
(p-channel), and I
MAX15024/MAX15025. For capacitive loads, the power
dissipation for each driver is:
where C
supply voltage, and FREQ is the switching frequency.
The MAX15024/MAX15025 MOSFET drivers source and
sink large currents to create very fast rise and fall edges
at the gate of the switching MOSFET. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. The following
LOAD
N_OUT CONNECTED
P = C
P = D x R
OR OUT1/OUT2
is the capacitive load, V
P_OUT AND
TOGETHER
LOAD
______________________________________________________________________________________
LOAD
IN+
ON(MAX)
is the output load current of the
x V
V
IL
DRV 2
Single/Dual, 16ns, High Sink/Source
Layout Information
Power Dissipation
x I
ON(MAX)
x FREQ
LOAD 2
DRV
t
D-OFF
is the maxi-
is the driver
90%
10%
t
F
printed-circuit board (PCB) layout guidelines are recom-
mended when designing with the MAX15024/MAX15025:
• Place one or more 1µF decoupling ceramic capaci-
• There are two AC current loops formed between the
• Keep the device as close as possible to the MOSFET.
• In the multilayer PCB, the inner layers should consist
tor(s) from V
possible. At least one storage capacitor of 10µF (min)
should be located on the PCB with a low resistance
path to the V
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from MOSFET gate to
OUT_ of the MAX15024/MAX15025 to PGND of the
MAX15024/MAX15025, and to the source of the
MOSFET. When the gate of the MOSFET is being
pulled high, the active current loop is from the V
terminal of the V
tor, to the V
OUT_ of the MAX15024/MAX15025, to the MOSFET
gate, to the MOSFET source, and to the negative ter-
minal of the decoupling capacitor. Both charging
current loop and discharging current loop are impor-
tant. It is important to minimize the physical distance
and the impedance in these AC current paths.
of a GND plane containing the discharging and
charging current loops.
Current Gate Drivers
DRV
CC
DRV
V
pin of the MAX15024/MAX15025.
IH
of the MAX15024/MAX15025, to the
DRV
to PGND as close to the device as
terminal of decoupling capaci-
t
D-ON
t
R
DD
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