MAX157 Maxim, MAX157 Datasheet - Page 9

• Manufacturer Part Number: MAX157
• Description: Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching Networks
• Manufacturer: Maxim

To start the conversion process on the MAX157/
MAX159, pull CS/SHDN low. At CS/SHDN’s falling
edge, the part wakes up, the internal T/H enters track
mode, and a conversion begins. In addition, the state of
SCLK at CS/SHDN’s falling edge selects internal (SCLK
= high) or external (SCLK = low) clock mode.
In internal clock mode, the MAX157/MAX159 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
5MHz. Operating the MAX157/MAX159 in internal clock
mode is necessary for serial interfaces operating with
clock frequencies lower than 100kHz or greater than
2.17MHz. Select internal clock mode (Figure 5) by hold-
Figure 4. Analog Input with Anti-Aliasing Filter Structure
Figure 5. Internal Clock Mode Timing
CS/SHDN
Internal Clock (f
DOUT
SCLK
ACTIVE
f
CORNER
= 15kHz
HIGH-Z
POWER
DOWN
t
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
CS
2
IN
SCLK
_______________________________________________________________________________________
ACTIVE
COM
SAMPLING INSTANT
0.01 F
1
MAX7410
MAX7414
t
(t
WAKE
< 100kHz or f
ACQ
V
)
OS
Selecting Clock Mode
DD
4
6
GND
SHDN
3
OUT
CLK
t
CONV
SCLK
7
5
8
> 2.17MHz)
1.5MHz
CLOCK
+2.7V, Low-Power, 2-Channel,
470
EOC
V
1
DD
1
2
1
3
0.1 F
CHID
0.01 F
ing SCLK high during a high/low transition of CS/SHDN.
The first SCLK falling edge samples the data and initi-
ates a conversion using the integrated on-chip oscilla-
tor. After the conversion, the oscillator shuts off and
DOUT goes high, signaling the end of conversion
(EOC). Data can then be read out with SCLK.
External clock mode (Figure 6) is selected by transition-
ing CS/SHDN from high to low while SCLK is low. The
external clock signal not only shifts data out, but also
drives the analog-to-digital conversion. The input is
sampled and conversion begins on the falling edge of
the second clock pulse. Conversion must be completed
within 140µs to prevent degradation in the conversion
results caused by droop on the T/H capacitors. External
clock mode provides the best throughput for clock fre-
quencies between 100kHz and 2.17MHz.
4
MSB
5
D8
6
2
3
8
External Clock (f
D7
CH0
CH1
SCLK
7
D6
8
MAX157
D5
9
GND
V
DD
D4
1
10
4
D3
CS/SHDN
11
DOUT
SCLK
D2
REF
12
D1
5
7
6
13
= 100kHz to 2.17MHz)
D0
14
S1
EXTERNAL
REFERENCE
15
S0
16
P/ C
HIGH-Z
9