ATA6826 ATMEL Corporation, ATA6826 Datasheet - Page 6

• Manufacturer Part Number: ATA6826
• Description: Triple Half-bridge DMOS Output Driver with Serial Input Control
• Manufacturer: ATMEL Corporation

3.2
3.3
3.4
3.5
3.6
6
Power-supply Fail
Open-load Detection
Overtemperature Protection
Short-circuit Protection
Inhibit
ATA6826
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set
and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the
undervoltage detection delay time t
age recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR
(Status Register Reset) bit in the input register.
If the current through a high-side or low-side switch in the ON-state stays below the open-load
detection threshold, the open-load detection bit (OPL) in the output register is set.
The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open
load, its duration has to be longer than the open-load detection delay time t
If the junction temperature of one or more output stages exceeds the thermal prewarning thresh-
old, T
temperature falls below the thermal prewarning threshold, T
bit can be read without transferring a complete 16-bit data word. The status of TP is available at
pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set
high and the data transfer is interrupted without affecting the status of input and output registers.
If the junction temperature of one or more output stages exceeds the thermal shutdown thresh-
old, T
low. The outputs can be enabled again when the temperature falls below the thermal shutdown
threshold, T
warning and shutdown threshold avoids oscillations.
The output currents are limited by a current regulator. Overcurrent detection is activated by writ-
ing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an
output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a
delay time (t
the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD
bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the
outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset
and the disabled outputs are enabled.
Applying 0V to pin 10 (INH) inhibits the ATA6826.
All output switches are then turned off and switched to tri-state. The data in the output register is
deleted. The current consumption is reduced to less than 5 µA at pin VS and less than 25 µA at
pin VCC. The output switches can be activated again by switching pin 10 (INH) to 5V which ini-
tiates an internal power-on reset.
j switch off
jPW set
jswitch on
dSd
, the temperature prewarning bit (TP) in the output register is set. When the
, all outputs are disabled and the corresponding bits in the output register are set to
). The short-circuit detection bit (SCD) is set and the corresponding status bit in
and the SRR bit in the input register is set to high. Hysteresis of thermal pre-
dUV
. The outputs are enabled immediately when supply volt-
jPW reset
, the bit TP is reset. The TP
dSd
.
4834C–BCD–06/06