MAX1761 Maxim, MAX1761 Datasheet - Page 21

• Manufacturer Part Number: MAX1761
• Description: Small / Dual / High-Efficiency Buck Controller for Notebooks
• Manufacturer: Maxim

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Figure 11. Feedback MUX
Figure 12. Setting V
FB1
When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Ensure that the OUT connection to C
and direct. However, in some cases it may be
desirable to deliberately introduce some trace
length between the OUT inductor node and the out-
put filter capacitor (see Stability Considerations).
Route high-speed switching nodes (CS_, DH_, and
DL_) away from sensitive analog areas (REF, FB_).
Use a PGND as an EMI shield to keep radiated
0.1V
OUT1
MAX1761
1/2
GND
OUT
DH
CS
FIXED
DL
FB
2.5V
OUT
______________________________________________________________________________________
with a Resistive Voltage-Divider
TO ERROR
AMP1
V+
MAX1761
TO ERROR
AMP2
FIXED
1.8V
R1
R2
Buck Controller for Notebooks
OUT
0.1V
is short
OUT2
Small, Dual, High-Efficiency
FB2
V
OUT
•
1) Place the power components first, with ground ter-
2) Mount the controller IC adjacent to the synchronous
3) Place the VL capacitor near the IC controller.
4) Make the DC-DC controller ground connections as
5) On the board’s top side (power planes), make a
6) Connect the output power planes directly to the out-
switching noise away from the IC, feedback
dividers, and analog bypass capacitors.
Avoid coupling switching noise into control input
connections (ON1, ON2, etc.). These pins should
be referenced to a quiet analog ground plane.
minals adjacent (Q2 source, CI
ble, make all these connections on the top layer
with wide, copper-filled areas.
rectifier MOSFETs, preferably on the back side in
order to keep CS_, PGND_, and the DL_ gate-drive
line short and wide. The DL_ gate trace must be
short and wide, measuring 10 to 20 squares (50mils
to 100mils wide if the MOSFET is 1 inch from the
controller IC).
follows: near the IC, create a small analog ground
plane. Use this plane for the ground connection for
the REF and VL bypass capacitor, and FB_
dividers. Create another small ground island for
PGND, and use it for the V+ bypass capacitor,
placed very close to the IC. Connect the AGND and
the PGND together under the IC (this is the only
connection between AGND and PGND).
star ground to minimize crosstalk between the two
sides. The top-side star ground is a star connection
of the input capacitors, side 1 low-side MOSFET,
and side 2 low-side MOSFET. Keep the resistance
low between the star ground and the sources of the
low-side MOSFETs for accurate current limit.
Connect the top-side star ground (used for MOS-
FET, input, and output capacitors) to the small
PGND island with a short, wide connection (prefer-
ably just a via). If multiple layers are available (high-
ly recommended), create PGND1 and PGND2
islands on the layer just below the top-side layer
(refer to the MAX1761 EV kit for an example) to act
as an EMI shield. Connect each of these individual-
ly to the star ground via, which connects the top
side to the PGND plane. Add one more solid
ground plane under the IC to act as an additional
shield, and also connect that to the star ground via.
put filter capacitor positive and negative terminals
with multiple vias.
Layout Procedure
N_
, C
OUT_
). If possi-
21