MAX199 Maxim, MAX199 Datasheet - Page 7

• Manufacturer Part Number: MAX199
• Description: Multi-Range (4V / 2V / +4V / +2V) / +5V Supply / 12-Bit DAS with 8+4 Bus Interface
• Manufacturer: Maxim

Figure 1. Reference-Adjust Circuit
______________________________________________________________Pin Description
16–23
7–10
PIN
11
12
13
14
15
24
25
26
27
28
1
2
3
4
5
6
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
100k
24k
+5V
CH0–CH7
REFADJ
D3/D11
D2/D10
NAME
D7–D4
SHDN
D1/D9
D0/D8
AGND
DGND
HBEN
CLK
REF
V
WR
INT
RD
CS
DD
510k
_______________________________________________________________________________________
0.01 F
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor (C
with C
Chip Select, active low.
When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.
When CS is low, a falling edge on RD will enable a read operation on the data bus.
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.
Three-State Digital I/O
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.
Analog Ground
Analog Input Channels
INT goes low when conversion is complete and output data is ready.
Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to V
Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to V
+5V Supply. Bypass with 0.1µF capacitor to AGND.
Digital Ground
CLK
= 100pF.
DD
REFADJ
when using an external reference at the REF pin.
Multi-Range (±4V, ±2V, +4V, +2V),
MAX199
CLK
) from this pin to ground to set the internal clock frequency; f
DD
.
Figure 2. Load Circuits for Enable Time
FUNCTION
D
OUT
a) High-Z to V
3k
OH
and V
OL
to V
C
LOAD
OH
b) High-Z to V
D
CLK
OUT
= 1.56MHz typical
3k
OL
+5V
and V
C
LOAD
OH
to V
OL
7