MAX3507EGI Maxim, MAX3507EGI Datasheet - Page 7

• Manufacturer Part Number: MAX3507EGI
• Description: Upstream CATV Amplifier with On-Chip Anti-Alias Filter
• Manufacturer: Maxim

The internal filter consists of an input transconductance
amplifier, a balanced fifth-order elliptic active lowpass
filter, and an offset-correction feedback network. The
signal at the output of the filter is level-shifted into the
programmable-gain amplifier.
The transconductance amplifier provides a high input
impedance to the user, and current drives the filter to
minimize insertion loss. The filter is a Gm-C topology to
provide sufficient bandwidth and linearity. The cutoff
frequency of the filter is fixed at 75MHz, while the spec-
ified stopband attenuation is met at 120MHz.
The internal offset-correction feedback network
removes any DC offset at the output of the filter. An off-
set voltage at this node would generate a transient dur-
ing a TX-enable or -disable transition, which would not
be acceptable. The offset-correction loop effectively
AC-couples the filter output to the programmable-gain
13, 15, 17, 20, 24
4, 8, 12, 23, 26
5, 22, 25
PIN
10
11
14
16
18
19
21
27
28
1
2
3
6
7
9
_______________________________________________________________________________________
NAME
BIASF
SHDN
OUT+
SCLK
CEXT
TXEN
OUT-
GND
DC+
SDA
N.C.
EQ+
V
DC-
EQ-
IN+
IN-
CS
Detailed Description
CC
Filter Bias. Connect to GND.
Filter Offset Correction. Connect 0.1µF capacitor between this pin and DC-.
Filter Offset Correction. Connect 0.1µF capacitor between this pin and DC+.
Ground
+5V Supply. Bypass this pin to GND with a 0.1µF capacitor as close to the part as possible.
Positive Input. Along with IN-, this port forms a high-impedance differential input to the filter.
Negative Input. When not used, this port must be AC-coupled to ground. See IN+.
Serial Interface Enable (Chip Select). TTL-compatible input. See Serial Interface section.
Serial Interface Data (Serial Data). TTL-compatible input. See Serial Interface section.
Serial Interface Clock (Serial Clock). TTL-compatible input. See Serial Interface section.
No Connection. Not internally connected.
Shutdown. When SHDN is set low, all functions (including the serial interface) are disabled.
RF Output Bypass. Bypass to ground with a 0.1µF capacitor.
Negative Output. Along with OUT+, this port forms a 300Ω impedance output. This port is matched
to a 75Ω load using a 2:1 (voltage ratio) transformer.
Positive Output. See OUT-.
Signal Path Enable. Setting this pin low turns off the PGA and power amplifier, leaving the filter
and serial interface enabled to save the last gain setting.
Positive Equalizer. Connect an RC network if equalization of the filter passband is desired; leave
open otherwise. See Typical Operating Characteristics.
Negative Equalizer. Connect an RC network if equalization of the filter passband is desired; leave
open otherwise. See Typical Operating Characteristics.
Internal Filter
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
amplifier input. The network generates a highpass cor-
ner frequency at:
Specified performance is achieved when the input is
driven differentially. The MAX3507 may be driven sin-
gle-ended. To drive the device in this manner, one of
the input pins must be capacitively coupled to ground.
Use a capacitor whose value is large enough to allow
for a low-impedance path to ground at the lowest fre-
quency of operation. For operation down to 5MHz, a
0.001µF capacitor is suggested.
The programmable-gain amplifier (PGA) consists of the
variable-gain amplifier (VGA) and the digital-to-analog
converter (DAC), which provide better than 55dB of
output-level control in 0.5dB steps. The PGA is imple-
mented as a programmable Gilbert-cell attenuator. It
uses a differential architecture to achieve maximum lin-
earity. The gain of the PGA is determined by a 7-bit
DESCRIPTION
f
-3dB
Programmable-Gain Amplifier
(kHz) = 12.5/C(µF)
Pin Description
7