MAX3540 Maxim Integrated Products, MAX3540 Datasheet - Page 6

• Manufacturer Part Number: MAX3540
• Description: Complete Single-Conversion Television Tuner
• Manufacturer: Maxim Integrated Products

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Complete Single-Conversion Television Tuner
The MAX3540 includes 11 programmable registers and
two read-only registers. The 11 programmable registers
include two N-divider registers, an R-divider register, a
VCO register, an RSSI/charge-pump/filter-select regis-
ter, a control register, a shutdown register, and tracking-
Table 1. Register Configuration
Table 2. N-DIV High Register (Address: 0000
6
Parallel Cap
Filter Select
Filter Series
REGISTER
N-DIV High
ROM Table
Pump, and
N-DIV Low
RESERVED
Filter ROM
Readback
BIT NAME
Shutdown
Reserved
IFOVLD,
Tracking
Tracking
Tracking
Address
Charge
Control
N[14:8]
NAME
Status
R-DIV
_______________________________________________________________________________________
VCO
Filter
Data
Cap
R EA D /
W R I T E
BIT LOCATION (0 = LSB)
Read
Read
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
REGISTER
ADDRESS
Detailed Description
6–0
0x0C
0x00
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x01
7
Register Descriptions
S H D N _M IX 1 S H D N _M IX 0 S H D N _I F S H D N _P D S H D N _S Y N
VCO4
TFR7
MSB
TFS7
POR
FLD
D7
N7
0
0
0
0
0
X
RECOMMENDED
DEFAULT
001 0010
0
IFOVLD2
VCO3
TFS6
TFR6
N14
LD2
D6
N6
R6
0
0
0
X
Must be set to 0.
Sets the most significant bits of the PLL integer divider (N). Default
integer divider value is N = 4688. N can range from 256 to 32,767.
IFOVLD1
b
VCO2
TFS5
TFP5
TFR5
)
N13
LD1
D5
N5
R5
filter control registers. These 11 programmable regis-
ters are also readable. The read-only registers include
a status register and a ROM table data register.
Recommended default bit settings are provided for
user convenience only and are not guaranteed. The
user must write all registers after power-up and no ear-
lier than 100μs after power-up.
X
0
0
IFOVLD0
DATA BYTE
VCO1
TFS4
TFP4
TFR4
N12
LD0
D4
N4
R4
0
0
X
SHDN_RF
VCO0
TFS3
TFP3
TFA3
TFR3
FUNCTION
N11
CP1
D3
N3
R3
X
X
SHDN_IFAGC INPT1 IN P T0
TFA2
TFR2
TFS2
TFP2
N10
CP0
D2
N2
R2
LD
X
X
0
VDIV1 V D IV 0
TFA1
TFR1
TFS1
TFP1
TF1
D1
N9
N1
R1
X
X
0
LSB
TFS0
TFP0
TFA0
TFR0
TF0
D0
N8
N0
R0
0
X
X