MAX3675ECJ Maxim, MAX3675ECJ Datasheet - Page 7

• Manufacturer Part Number: MAX3675ECJ
• Description: 622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
• Manufacturer: Maxim

The block diagram in Figure 1 shows the MAX3675’s
architecture. It consists of a limiting amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a phase-locked loop
(PLL). The input stage is selectable between a limiting
amplifier or a simple PECL input buffer. The limiting
amplifier provides a loss-of-power (LOP) monitor and a
received-signal-strength indicator (RSSI). The PLL con-
sists of a phase/frequency detector (PFD), a loop filter
amplifier, and a voltage-controlled oscillator (VCO).
The MAX3675’s on-chip limiting amplifier accepts an
input signal level from 3.0mVp-p to 1.2Vp-p. The ampli-
fier consists of a cascade of gain stages that include
full-wave logarithmic detectors. The combined small-
signal gain is approximately 42dB, and the -3dB band-
width is 800MHz. Input-referred noise is less than
Figure 1. Functional Diagram
_______________Detailed Description
INSEL
DDI+
ADI+
DDI-
ADI-
and Data-Retiming IC with Limiting Amplifier
622Mbps, Low-Power, 3.3V Clock-Recovery
PECL
LIMITER
42dB
OLC+
CORRECTION
_______________________________________________________________________________________
OFFSET
LOL
OLC-
V
6k
CC
DETECT
POWER
CFILT
Limiting Amplifier
BIAS
RSSI
1.18V
PHASE/FREQ
INV
DETECTOR
VTH
PHADJ+
100µV
amplitude data streams.
In addition to driving the CDR, the limiting amplifier pro-
vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mVp-p.
Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC coupled when
using the ADI+ and ADI- inputs.
Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the post-amplifier block.
PHADJ-
RMS
FIL+ FIL-
FILTER
, providing excellent sensitivity for small-
V
6k
LOP
CC
622.08MHz
VCO
MAX3675
Q
I
D
Q
PECL
PECL
SDO+
SDO-
SCLKO+
SCLKO-
7