MAX3941 Maxim, MAX3941 Datasheet - Page 8

• Manufacturer Part Number: MAX3941
• Description: 10Gbps EAM Driver with Integrated Bias Network
• Manufacturer: Maxim

The MAX3941 EAM driver consists of two main parts: a
high-speed modulation driver and an EAM-biasing
block. The clock and data inputs to the driver are com-
patible with PECL and CML logic levels. The modula-
tion and bias currents are output through the OUT pin.
The modulation output stage is composed of a high-
speed differential pair and a programmable current
source with a maximum modulation current of 120mA.
The rise and fall times are typically 23ps. The modulation
current is designed to produce an EAM voltage up to
3.0V
from 120mA
50Ω EAM load and the internal 50Ω back termination.
10Gbps EAM Driver with Integrated
Bias Network
8
7, 11, 12, 13,
18, 19, 24
_______________________________________________________________________________________
P-P
3, 4, 14
PIN
EP
10
15
16
17
20
21
22
23
1
2
5
6
8
9
when driving a 50Ω module. The 3.0V
P-P
through the parallel combination of the
MODSET
BIASSET
Exposed
MODEN
DATA+
NAME
DATA-
PWC+
GND1
GND2
CLK+
PWC-
RTEN
PLRT
GND
CLK-
OUT
Pad
V
EE
Detailed Description
Noninverting Data Input with 50Ω On-Chip Termination
Inverting Data Input with 50Ω On-Chip Termination
Ground. All pins must be connected to board ground.
Noninverting Clock Input for Data Retiming with 50Ω On-Chip Termination
Inverting Clock Input for Data Retiming with 50Ω On-Chip Termination
Negative Supply Voltage. All pins must be connected to board V
Positive Input for Modulation Pulse-Width Adjustment (See the Design Procedure Section)
Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width
adjustment feature (see the Design Procedure section).
Modulation Current Set. Apply a voltage to set the modulation current of the driver output.
Ground. Ground connection.
Driver Output. Provides both modulation and bias output. DC-couple to EAM.
Ground. Ground connection.
Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the
differential signal polarity. Contains an internal 100kΩ pullup to GND.
Bias Current Set. Apply a voltage to set the bias current of the driver output.
TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM
in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to V
Data-Retiming Input. Connect to V
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance
(see the Exposed Pad Package section).
P-P
results
EE
for retimed data. Connect to GND to bypass retiming latch.
The MAX3941 includes a polarity switch. When the
PLRT pin is high or left floating, the output maintains the
polarity of the input data. When the PLRT pin is low, the
output is inverted relative to the input data.
The MAX3941 is directly compatible with ground-refer-
ence CML. Either DC- or AC-coupling can be used for
CML referenced to ground. For all other logic types,
AC-coupling should be used.
To reject pattern-dependent jitter in the input data, a syn-
chronous differential clock signal should be connected to
the CLK+ and CLK- inputs, and the RTEN control input
should be connected to V
FUNCTION
Clock/Data Input Logic Levels
Optional Data Input Latch
EE
EE
.
.
Pin Description
EE
.
Polarity Switch