WM8143-12 Wolfson Microelectronics Ltd., WM8143-12 Datasheet - Page 6

• Manufacturer Part Number: WM8143-12
• Description: WM8143 : 10 or 12-BIT, 4MSPS Analogue Front End For CCD Image Sensors
• Manufacturer: Wolfson Microelectronics Ltd.

WM8143-12
Pin Description
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
SCK/RNW
SEN/STB
NRESET
SDI/DNA
NAME
OP[10]
OP[11]
AGND
VSMP
AVDD
VRLC
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]
VMID
GINP
BINP
RINP
VRU
VRB
VRT
OEB
RLC
Analogue supply
Analogue supply
Analogue OP
Analogue OP
Analogue OP
Analogue OP
Analogue IP
Analogue IP
Analogue IP
Analogue IP
Digital OP
Digital OP
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IP
Digital IP
Digital IP
Digital IP
Digital IP
Digital IP
Digital IP
TYPE
Wolfson Microelectronics
Tri-state digital 12-bit bi-directional bus. There are four modes:
Tri-state:
Output twelve-bit:
Output 8-bit multiplexed:
Input 8-bit:
MSB of the output word is OP[11], LSB is OP[0]
Reset input, active low. This signal forces a reset of all internal registers and selects
whether the serial control bus or parallel control bus is used (see SEN/STB)
Positive analogue supply (5V)
Analogue ground (0V)
ADC reference voltages. The ADC reference range is applied between VRT (full
scale) and VRB (zero level). VRU can be used to derive optimal reference voltages
from an external 5V reference
Buffered mid-point of ADC reference string
Selectable analogue output voltage for RLC
Blue channel input video
Green channel input video
Red channel input video
Output tri-state control:
Serial interface:
Parallel interface:
Latched on NRESET rising edge: If low then device control is by serial interface, if
high then device control is by parallel interface
Serial interface:
Parallel interface:
Serial interface:
Parallel interface:
Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is
required on each pixel then this pin can be tied high
Video sample synchronisation pulse. This signal is applied synchronously with
MLCK to specify the point in time that the input is sampled. The timing of internal
multiplexing between the R, G and B channels is derived from this signal.
6
DESCRIPTION
when OEB = 1
twelve bit data is output from bus
data output on OP[11:4] at 2 * ADC
conversion Rate
control data is input on bits OP[11:4] in
parallel mode when SCK/RNW = 0.
all outputs enabled when OEB = 0
enable, active high
strobe, active low
serial interface input data signal
high = data, low = address
serial interface clock signal
high = OP[11:4] is output bus
low = OP[11:4] is input bus
PD. Rev 4 Nov 99
Production Data