WM8148 Wolfson Microelectronics Ltd., WM8148 Datasheet - Page 9
![no-image](/images/no-image-200.jpg)
WM8148
Manufacturer Part Number
WM8148
Description
WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser
Manufacturer
Wolfson Microelectronics Ltd.
Datasheet
1.WM8148.pdf
(43 pages)
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WM8148
RESET LEVEL CLAMP
Figure 3 Reset Level Clamp Control Timing
Figure 4 Internal Clamp Signal (CL) Timing
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, T
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
Notes: 1. Internal clamp signal (CL) timing may be relative to either the falling or rising edge of MCLK depending on the setting of
WOLFSON MICROELECTRONICS LTD
PARAMETER
MCLK period
Propagation delay
Set-up time
Hold time
C L
C L
C L
C L
RLC = 0
RLC = 1
MCLK
VSMP
2. Parameters are measured at 50% of the rising/falling edge.
MODE 8-13
MODE 8-13
control bits RESREF[3:0].
SMALL = 0
SMALL = 1
SMALL = 0
SMALL = 1
MODE 0-5
MODE 0-5
M C L K
O F F
SYMBOL
t
t
t
t
RLCPD
RLCSU
O F F
RLCH
PER
t
RLCPD
O F F
TEST CONDITIONS
t
RLCSU
O F F
t
RLCPD
t
PER
t
RLCPD
20.8
MIN
t
10
10
RLCH
O N
A
= 0 to 70 C, MCLK = 48MHz unless
O N
t
RLCPD
TYP
15
O N
MAX
O N
t
t
t
t
PD Rev 4.0 April 1999
RLCPD
RLCPD
RLCPD
RLCPD
Production Data
UNITS
O F F
O F F
O F F
O F F
ns
ns
ns
ns
9
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