WM8731 Wolfson Microelectronics Ltd., WM8731 Datasheet - Page 32

• Manufacturer Part Number: WM8731
• Description: WM8731 : Low Power Audio Codec With Integrated Headphone Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8731
CRYSTAL OSCILLATOR
The WM8731 includes a crystal oscillator circuit that allows the audio system’s reference clock to be
generated on the device. This is available to the rest of the audio system in buffered form on
CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application
circuit is shown in Figure 24.
Figure 24 Crystal Oscillator Application Circuit
For crystal frequencies in the 12MHz range, a Cp of 10pF is recommended. For crystal frequencies
in the 18MHz range, 15pF Cp is recommended.
The WM8731 crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a
requirement for high quality audio ADC and DACs, regardless of the converter architecture. The
WM8731 architecture is less susceptible than most converter techniques but still requires clocks with
less than approximately 1ns of jitter to maintain performance. In applications where there is more
than one source for the master clock, it is recommended that the clock is generated by the WM8731
to minimise such problems.
CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the
CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for
driving external loads.
There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will
inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to
Electrical Characteristics.
CLKOUT can also be divided by 2 under software control, refer to Table 13. Note that if CLKOUT is
not required then the CLKOUT buffer on the WM8731 can be safely powered down to conserve
power (see POWER DOWN section). If the system architect has the choice between using F
F
divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
Table 13 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
MCLK
0001000
Sampling
Control
REGISTER
ADDRESS
or F
Cp
XTI/MCLK
CLKOUT
DGND
= F
7
BIT
MCLK
/2 in the interface, the latter is recommended to conserve power. When the
CLKODIV2
LABEL
DGND
XTO
Cp
0
DEFAULT
CLKOUT divider select
1 = CLOCKOUT is Core Clock
divided by 2
0 = CLOCKOUT is Core Clock
DESCRIPTION
AI Rev 2.3 August 2001
Advanced Information
CLKOUT
32
=