MAX5132 Maxim, MAX5132 Datasheet - Page 13

• Manufacturer Part Number: MAX5132
• Description: +5V/+3V / 13-Bit / Serial / Force/Sense DACs with 10ppm/C Internal Reference
• Manufacturer: Maxim

The MAX5132/MAX5133 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by
initializing its synchronous serial-port control register
(SSPCON) and synchronous serial-port status register
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit writings (Figure
6) are necessary to feed the DAC with three control bits
and 13 data bits. DIN data transitions on the serial
clock’s falling edge and is clocked into the DAC on
SCLK’s rising edge. The first eight bits of DIN contain
Table 2. Serial Data Format
Figure 6. Serial-Interface Timing
Figure 7. Detailed Serial-Interface Timing
MSB ........................................... LSB
DOUT
SCLK
Control Bits
C2, C1, C0
DIN
CS
+5V/+3V, 13-Bit, Serial, Force/Sense DACs
SCLK
DIN
CS
16 BITS OF SERIAL DATA
______________________________________________________________________________________
C2
t
CS0
1
C1
D12................................D0
MSB ..... Data Bits ..... LSB
PIC16 with SSP Module
C0 D12 D11 D10 D9
with 10ppm/°C Internal Reference
and PIC17 Interface
t
CSS
t
DS
D8
t
DO1
8
t
CH
D7
t
CSH
the three control bits (C2, C1, C0) and the first five data
bits (D12–D8). The second 8-bit data stream contains
the remaining bits, D7–D0.
The contents of the internal shift-register are output seri-
ally on DOUT, which allows for daisy-chaining (see
Applications Information ) of multiple devices as well as
data readback. The MAX5132/MAX5133 may be pro-
grammed to shift data out of DOUT on the serial clock’s
rising edge (Mode 1) or on the falling edge (Mode 0).
The latter is the default during power-up and provides a
lag of 16 clock cycles, maintaining SPI, QSPI,
MICROWIRE, and PIC16/PIC17 compatibility. In Mode
1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1),
thereby reducing the number of microcontroller I/O
ports required. During power-down, this output will
retain the last digital state before shutdown. With CLR
pulled low, UPO will reset to the default state after
wake-up.
9
D6
t
CP
D5
t
DO2
D4
t
CL
User-Programmable Output (UPO)
D3
D2
t
CS1
D1
t
DH
D0
16
t
CSW
Serial Data Output
COMMAND
EXECUTED
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