CORE429-AN Actel Corporation, CORE429-AN Datasheet - Page 16

• Manufacturer Part Number: CORE429-AN
• Description: Arinc 429 Bus Interface
• Manufacturer: Actel Corporation

CPU Interface Timing for Default Mode
The CPU interface signals are synchronized to the Core429 master clock.
the waveforms for the CPU interface.
Note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available one cycle after cpu_ren
Figure 7 •
Note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. The write is done two cycles after cpu_wen is
Figure 8 •
Note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available six cycles after cpu_ren
Figure 9 •
Note:
Figure 10 •
1 6
cpu_dout[31:0]
ARINC 429 Bus Interface
cpu_add[8:0]
cpu_wait
is sampled.
sampled.
is sampled.
sampled.
cpu_ren
cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. The write is done two cycles after cpu_wen is
clk
CPU Interface Control/Status Register Read Cycle
CPU Interface Control Register Write Cycle
CPU Interface Data Register Read Cycle
CPU Interface Data Register Write Cycle
cpu_din[31:0]
cpu_dout[31:0]
cpu_add[8:0]
cpu_din[31:0]
cpu_add[8:0]
cpu_add[8:0]
cpu_wait
cpu_wen
cpu_wen
cpu_wait
cpu_wait
cpu_ren
clk
clk
clk
A DDR
A DDR
A DDR
A DDR
Data
v5.0
Data
Write Done
Write
Figure 7
through
Figure 12 on page 17
Data
show