AT91M40807 ATMEL Corporation, AT91M40807 Datasheet - Page 9

• Manufacturer Part Number: AT91M40807
• Description: At91 Arm(r) Thumb(r) Microcontroller
• Manufacturer: ATMEL Corporation

JTAG/ICE Debug
Memory Controller
Internal Memories
Boot Mode Select
Remap Command
1371CS–ATARM–02/02
ARM Standard Embedded In Circuit Emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI Core responds with a non-JTAG chip ID that iden-
tifies the microcontroller. This is not fully IEEE1149.1 compliant.
The ARM7TDMI microcontroller address space is 4G bytes. The memory controller
decodes the internal 32-bit address bus and defines three address spaces:
•
•
•
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
The AT91M40807 microcontroller integrates internal static SRAM and ROM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-
bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching
Thumb or ARM instructions is supported and internal memory can store twice as many
Thumb instructions as ARM ones.
The 8K-byte primary SRAM bank is mapped at address 0 x 0 (after the remap com-
mand), allowing ARM7TDMI exception vectors between 0 x 0 and 0 x 20 to be modified
by the software. The rest of the bank can be used for stack allocation (to speed up con-
text saving and restoring), or as data and program storage for critical algorithms.
The 128K bytes of internal ROM are mapped at address 0 x 0010 0000. The ROM ver-
sions offer a reduced-cost option of the AT91R40807 for high-volume applications in
which the software is stable.
The AT91R40807 microcontroller integrates an extended SRAM memory bank of 128K
bytes that can be used to validate the code to be stored in the on-chip ROM memory
prior to manufacture of the AT91M40807.
The ARM reset vector is at address 0 x 0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in non-volatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory. The Boot Mode depends on BMS (see
Table 3).
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like
any standard PIO line.
Table 3. Boot Mode Select
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,
Interrupt and Fast Interrupt) are mapped from address 0 x 0 to address 0 x 20. In order
to allow these vectors to be redefined dynamically by the software, the AT91M40807
microcontroller uses a remap command that enables switching between the boot mem-
BMS
1
0
Internal Memories in the four lowest megabytes
Middle Space reserved for the external devices (memory or peripherals) controlled
by the EBI
Internal Peripherals in the four highest megabytes
Boot Memory
Internal 32-bit ROM
External 16-bit memory on NCS0
AT91M40807
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