FLASH6-C3 Austria Mikro Systeme International AG, FLASH6-C3 Datasheet - Page 6

• Manufacturer Part Number: FLASH6-C3
• Description: Analog IP Block Flash6 - CMOS 6-bit Flash A/D Converter
• Manufacturer: Austria Mikro Systeme International AG

Data Sheet : FLASH6 - C35
SYMBOL
THEORY OF OPERATION
The Macro Cell FLASH6 is a 6-bit single step parallel analog to
digital converter. The architecture is based on a 380 Ohm
polysilicon resistor reference ladder and static CMOS comparators.
The thermometer code of the comparator outputs is encoded in a
fast ROM encoder into straight binary code with CMOS logic signal
levels. The last comparator output is connected unlatched to the
OVL output. The area of the converter is small. The comparators do
not need auto zeroing and therefore are fast and perform minimal
kickback on the analog signal input. The conversion range is set by
the reference inputs VREFP and VREFN. The output OVL indicates
an overload condition when Vin > (VREFP - 0.5*LSB).
POWER SUPPLIES
The converter requires a single +3.3V power supply. The supplies
for analog and digital are separated and may be connected
together. However, for maximum noise immunity it is
Revision B, 07.09.02
VREFP
VREFN
IBIAS
CLK
SHIELD
VIN
PD
VDDA
FLASH6
VSSA
A
D
VDD
VSS
6
DATA<5:0>
OVL
STROBE
PINLIST
Pin
VIN
VREFP
VREFN
IBIAS
PD
CLK
DATA<5:0>
OVL
STROBE
VDDA
VSSA
SHIELD
VDD
VSS
recommended to wire them on chip to separated pins, especially
when the block is embedded in a large digital circuit. The supplies
may then be connected together on PC-board level.
The proper use of blocking capacitors in the application is important
REFERENCE VOLTAGE
Both input pads VREFP and VREFN must have a 0 Ohm protection
resistor. The ESD test was performed with 1kV (Norm: MIL 883 E
method 3015).
The proper use of blocking capacitors in the application is
INPUT VOLTAGE
The input pad VIN must have a 0 Ohm protection resistor. The ESD
test was performed with 1kV (Norm: MIL 883 E method 3015).
important !
Description
Input Voltage
Pos. Reference
Voltage
Neg. Reference
Voltage
Bias Current
Power down
Signal
Master Clock
Data Output
(DATA<5>=MSB)
Overload
Data Strobe Signal
Pos. Analog
Supply
Neg. Analog
Supply
Connect to VSSA
Pos. Digital
Supply
Neg. Digital
Supply
Page 6 of 9
Typ
AIN
AIN
AIN
AIN
DIN
DIN
DOUT
DOUT
DOUT
S
S
S
S
S
Cap
5pF
0.1pF
0.1pF