MAX705 Maxim, MAX705 Datasheet - Page 6

• Manufacturer Part Number: MAX705
• Description: Low-Cost / uP Supervisory Circuits
• Manufacturer: Maxim

A microprocessor’s (µP’s) reset input starts the µP in a
known state. Whenever the µP is in an unknown state, it
should be held in reset. The MAX705-MAX708/MAX813L
assert reset during power-up and prevent code execu-
tion errors during power-down or brownout conditions.
On power-up, once V
teed logic low of 0.4V or less. As V
low. When V
nal timer releases RESET after about 200ms. RESET puls-
es low whenever V
brownout condition. If brownout occurs in the middle of
a previously initiated reset pulse, the pulse continues for
at least another 140ms. On power-down, once V
below the reset threshold, RESET stays low and is guar-
anteed to be 0.4V or less until V
The MAX707/MAX708/MAX813L active-high RESET output
is simply the complement of the RESET output, and is
guaranteed to be valid with V
such as Intel’s 80C51, require an active-high reset pulse.
The MAX705/MAX706/MAX813L watchdog circuit moni-
tors the µP’s activity. If the µP does not toggle the watch-
dog input (WDI) within 1.6sec and WDI is not three-stat-
ed, WDO goes low. As long as RESET is asserted or the
Low-Cost, µP Supervisory Circuits
Figure 1. MAX705/MAX706/MAX813L Block Diagram
_______________Detailed Description
6
* 4.40V FOR MAX7O6.
( ) ARE FOR MAX813L ONLY.
V
WDI
MR
PFI
CC
_______________________________________________________________________________________
1
2
4
6
V
CC
WATCHDOG
TRANSITION
DETECTOR
250 A
1.25V
4.65V*
CC
rises above the reset threshold, an inter-
CC
CC
dips below the reset threshold, i.e.
reaches 1V, RESET is a guaran-
3
TIMEBASE FOR
GENERATOR
CC
WATCHDOG
WATCHDOG
RESET AND
RESET
TIMER
GND
MAX813L
MAX705
MAX706
CC
down to 1.1V. Some µPs,
drops below 1V.
Watchdog Timer
CC
rises, RESET stays
Reset Output
8
7
5
CC
PFO
WDO
RESET
(RESET)
falls
WDI input is three-stated, the watchdog timer will stay
cleared and will not count. As soon as reset is released
and WDI is driven high or low, the timer will start counting.
Pulses as short as 50ns can be detected.
Typically, WDO will be connected to the non-maskable
interrupt input (NMI) of a µP. When V
the reset threshold, WDO will go low whether or not the
watchdog timer has timed out yet. Normally this would
trigger an NMI interrupt, but RESET goes low simultane-
ously, and thus overrides the NMI interrupt.
If WDI is left unconnected, WDO can be used as a low-
line output. Since floating WDI disables the internal
timer, WDO goes low only when V
reset threshold, thus functioning as a low-line output.
The MAX705/MAX706 have a watchdog timer and a
RESET output. The MAX707/MAX708 have both active-
high and active-low reset outputs. The MAX813L has
both an active-high reset output and a watchdog timer.
The manual-reset input (MR) allows reset to be trig-
gered by a pushbutton switch. The switch is effectively
debounced by the 140ms minimum reset pulse width.
MR is TTL/CMOS logic compatible, so it can be driven
by an external logic line. MR can be used to force a
watchdog timeout to generate a reset pulse in the
MAX705/MAX706/MAX813L. Simply connect WDO to
MR.
Figure 2. MAX707/MAX708 Block Diagram
V
MR
PFI
CC
* 4.40V FOR MAX7O6.
1
2
4
V
CC
250 A
1.25V
4.65V*
3
GENERATOR
RESET
GND
MAX707
MAX708
CC
Manual Reset
CC
falls below the
drops below
8
7
5
RESET
RESET
PFO