MAX7408 Maxim, MAX7408 Datasheet - Page 9

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MAX7408

Manufacturer Part Number
MAX7408
Description
5th-Order / Lowpass / Elliptic / Switched-Capacitor Filters
Manufacturer
Maxim
Datasheet

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Figure 2. Elliptic Filter Response
These SCFs are designed for use with external clocks
that have a 40% to 60% duty cycle. When using an
external clock, drive the CLK pin with a CMOS gate
powered from 0 to V
clock adjusts the corner frequency of the filter:
When using the internal oscillator, the capacitance
(C
Since C
capacitance at CLK so that it does not affect the inter-
nal oscillator frequency. Varying the rate of the internal
oscillator adjusts the filter’s corner frequency by a
100:1 clock-to-corner frequency ratio. For example, an
internal oscillator frequency of 100kHz produces a
nominal corner frequency of 1kHz.
The MAX7408/MAX7411/MAX7412/MAX7415’s input
impedance is effectively that of a switched-capacitor
resistor (see the following equation), and is inversely
proportional to frequency. The input impedance values
determined by the equation represent the average input
impedance, since the input current is not continuous. As
a rule, use a driver with an output resistance less than
10% of the filter’s input impedance.
OSC
Input Impedance vs. Clock Frequencies
) on CLK determines the oscillator frequency:
OSC
is in the low picofarads, minimize the stray
PASSBAND
f
OSC
_______________________________________________________________________________________
(kHz)
f
C
DD
f
C
. Varying the rate of the external
f
C
TRANSITION RATIO =
f
S
f
100
CLK
C
27
RIPPLE
f
OSC
S
10
(pF)
STOPBAND
FREQUENCY
3
Clock Signal
External Clock
f
f
Internal Clock
S
C
5th-Order, Lowpass, Elliptic,
Switched-Capacitor Filters
Estimate the input impedance of the filter by using the
following formula:
where f
The MAX7408/MAX7411/MAX7412/MAX7415 have a
shutdown mode that is activated by driving SHDN low.
In shutdown mode, the filter supply current reduces to
0.2µA, and the output of the filter becomes high imped-
ance. For normal operation, drive SHDN high or con-
nect to V
COM sets the common-mode input voltage and is
biased at mid-supply with an internal resistor-divider. If
the application does not require offset adjustment, con-
nect OS to COM. For applications where offset adjust-
ment is required, apply an external bias voltage
through a resistor-divider network to OS, as shown in
Figure 3. For applications that require DC level shifting,
adjust OS with respect to COM. (Note: Do not leave OS
unconnected.) The output voltage is represented by
these equations:
where (V
OS is added at the output stage. See the Electrical
Figure 3. Offset Adjustment Circuit
0.1 F
CLOCK
INPUT
CLK
Offset (OS) and Common-Mode (COM)
V
DD
IN
SUPPLY
.
- V
= clock frequency and C
V
V
OUT
COM
COM
Applications Information
Z
IN
CLK
IN
) is lowpass filtered by the SCF and
Low-Power Shutdown Mode
(
MAX7408
MAX7411
MAX7412
MAX7415
V
V
IN
(f
DD
V
GND
2
DD
CLK
(
typical
1
V
COM
SHDN
COM
C )
OUT
Input Adjustment
OS
IN
)
)
IN
0.1 F
0.1 F
= 1pF.
V
OS
OUTPUT
50k
50k
50k
9

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