MAX7418 Maxim, MAX7418 Datasheet - Page 11

• Manufacturer Part Number: MAX7418
• Description: 5th-Order / Lowpass / Switched-Capacitor Filters
• Manufacturer: Maxim

Figure 3. Bessel vs. Butterworth Filter Response
When using the internal oscillator, the capacitance
(C
where
k = 87 x 10
MAX7418/MAX7421/MAX7422/MAX7425
and
k = 110 x 10
MAX7419/MAX7420/MAX7423/ MAX7424.
Since C
capacitance at CLK so that it does not affect the inter-
nal oscillator frequency. Varying the rate of the internal
oscillator adjusts the filter’s corner frequency by a
100:1 clock-to-corner frequency ratio. For example, an
internal oscillator frequency of 2.2MHz produces a
nominal corner frequency of 2.2kHz.
The MAX7418–MAX7425s’ input impedance is effective
as a switched-capacitor resistor and is inversely propor-
tional to frequency. The input impedance values deter-
mined by the equation represents the average input
impedance, since the input current is not continuous.
As a rule, use a driver with an output resistance less
than 10% of the filter’s input impedance.
Estimate the input impedance of the filter by using the
following formula:
OSC
Input Impedance vs. Clock Frequencies
) on CLK determines the oscillator frequency:
OSC
C
3
A
B
A: 1kHz INPUT SIGNAL
B: MAX7419 BESSEL FILTER RESPONSE; f
C: MAX7420 BUTTERWORTH FILTER RESPONSE; f
3
for the
is in the low picofarads, minimize the stray
for the
f OSC (kHz)
______________________________________________________________________________________
200µs/div
=
C OSC (pF)
k
C
= 5kHz
C
Internal Clock
= 5kHz
2V/div
2V/div
2V/div
Switched-Capacitor Filters
where f
The MAX7418–MAX7425 have a shutdown mode that is
activated by driving SHDN low. In shutdown mode, the
filter supply current reduces to 0.2µA, and the output of
the filter becomes high impedance. For normal opera-
tion, drive SHDN high or connect to V
COM sets the common-mode input voltage and is
biased at midsupply with an internal resistor-divider. If
the application does not require offset adjustment, con-
nect OS to COM. For applications in which offset
adjustment is required, apply an external bias voltage
through a resistor-divider network to OS, as shown in
Figure 4. For applications that require DC level shifting,
adjust OS with respect to COM. (Note: Do not leave OS
unconnected.) The output voltage is represented by
these equations:
where (V
OS is added at the output stage. See the Electrical
Characteristics table for the input voltage range of COM
Figure 4. Offset Adjustment Circuit
0.1µF
CLOCK
INPUT
5th-Order, Lowpass,
Offset (OS) and Common-Mode (COM)
CLK
V
IN
SUPPLY
- V
= clock frequency and C
V
V
OUT
COM
COM
IN
CLK
Applications Information
Z
IN
) is lowpass filtered by the SCF and
Low-Power Shutdown Mode
=
=
MAX7418–
=
MAX7425
(
V
V
GND
V
DD
(f
IN
DD
2
CLK
−
(
typ
SHDN
V
1
COM
×
OUT
COM
OS
)
C )
Input Adjustment
IN
0.1µF
0.1µF
)
IN
DD
+
OUTPUT
= 1pF.
V
.
OS
50k
50k
50k
11