MCIMX31 Motorola Semiconductor Products, MCIMX31 Datasheet - Page 35

• Manufacturer Part Number: MCIMX31
• Manufacturer: Motorola Semiconductor Products

4.3.8
The three PLL’s of the i.MX31 (MCU, USB, and Serial PLL) are all based on same DPLL design. The
characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics
are provided based on measurements done for both sources—external clock source (CKIH), and FPM
(Frequency Pre-Multiplier) source.
4.3.8.1
Table 31
Freescale Semiconductor
1
CKIH frequency
CKIL frequency
(Frequency Pre-multiplier (FPM) enable mode)
Predivision factor (PD bits)
PLL reference frequency range after Predivider
PLL output frequency range:
Maximum allowed reference clock phase noise.
Frequency lock time
(FOL mode or non-integer MF)
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
CS10
CS11
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
ID
lists the DPLL specification.
DPLL Electrical Specifications
SCLK Cycle Time
SCLK High or Low Time
SCLK Rise or Fall
SSx pulse width
SSx Lead Time (CS setup time)
SSx Lag Time (CS hold time)
Data Out Setup Time
Data Out Hold Time
Data In Setup Time
Data In Hold Time
SPI_RDY Setup Time
Electrical Specifications
Parameter
MPLL and SPLL
1
MCIMX31/MCIMX31L Advance Information, Rev. 3.2
Parameter
Table 30. CSPI Interface Timing Parameters
Preliminary—Subject to Change Without Notice
UPLL
Table 31. DPLL Specifications
Min
190
15
15
52
—
—
—
1
32; 32.768, 38.4
Typ
26
—
—
—
—
—
1
t
RISE/FALL
Symbol
t
t
t
t
t
t
t
t
Smosi
Hmosi
Smiso
Hmiso
CSLH
SRDY
t
HCS
SCS
t
SW
clk
±
Max
532
240
398
75
16
35
—
100
2
MHz
MHz 15 ≤ CKIH frequency/PD ≤ 35 MHz
MHz
Unit
kHz FPM lock time ≈ 480 µs.
—
ps
—
Min
15 ≤ FPM output/PD ≤ 35 MHz
Cycles of divided reference clock.
60
30
25
25
25
—
—
5
5
6
5
Electrical Characteristics
Comments
Max
7.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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