MAX817 Maxim, MAX817 Datasheet - Page 10

• Manufacturer Part Number: MAX817
• Description: +5V Microprocessor Supervisory Circuits
• Manufacturer: Maxim

+5V Microprocessor Supervisory Circuits
On the MAX819, MR must be high or open to enable
the battery freshness seal. Once the battery freshness
seal is enabled its operation is unaffected by MR.
In the MAX817/MAX818, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watchdog
input (WDI) within t
nal 1.6sec timer is cleared by either a reset pulse or by
toggling WDI, which can detect pulses as short as
50ns. The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is
released, the timer starts counting (Figure 4).
To disable the watchdog function, leave WDI uncon-
nected or three-state the driver connected to WDI. The
watchdog input is internally driven low during the first
7/8 of the watchdog timeout period, then momentarily
pulses high, resetting the watchdog counter. When
WDI is left open-circuited, this internal driver clears the
1.6sec timer every 1.4sec. When WDI is three-stated or
left unconnected, the maximum allowable leakage cur-
rent is 10µA and the maximum allowable load capaci-
tance is 200pF.
Internal gating of the chip-enable (CE) signal prevents
erroneous data from corrupting CMOS RAM in the
event of an undervoltage condition. The MAX818 uses
a series transmission gate from CE IN to CE OUT
(Figure 5). During normal operation (reset not assert-
ed), the CE transmission gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short CE propagation
delay from CE IN to CE OUT enables the MAX818 to be
used with most µPs. If CE IN is low when reset asserts,
CE OUT remains low for typically 15µs to permit the
current write cycle to complete.
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when V
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate will disable 15µs after reset
asserts (Figure 6). This permits the current write cycle
to complete during power-down.
10
______________________________________________________________________________________
Watchdog Input (MAX817/MAX818)
Chip-Enable Gating (MAX818)
WD
Chip-Enable Input (MAX818)
(1.6sec), reset asserts. The inter-
CC
passes the
Figure 4. Watchdog Timing
Figure 5. Chip-Enable Transmission Gate
Figure 6. Chip-Enable Timing
CE IN
V
RESET
V
CE OUT
V
RESET
WDI
V
CE IN
V
CC
CC
V
BATT
CHIP-ENABLE
GENERATOR
t
CONTROL
RP
OUTPUT
MAX817
MAX818
V
RESET
RST
t
RP
V
RST
SEAL CIRCUITRY
V
FRESHNESS
P
N
BATT
BATTERY
15 s
SWITCHOVER
t
RP
CIRCUITRY
V
BATTERY
RST
OUT
V
RST
t
WD
CE OUT