MAX9160EUI Maxim, MAX9160EUI Datasheet

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MAX9160EUI

Manufacturer Part Number
MAX9160EUI
Description
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Manufacturer
Maxim
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
MAX9160EUI
Manufacturer:
MAXIM/美信
Quantity:
20 000
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock
driver repeats the selected LVDS or LVTTL/LVCMOS
input on two output banks. Each bank consists of seven
LVTTL/LVCMOS series terminated outputs and a bank
enable. The LVDS input has a fail-safe function. The
MAX9160 has a propagation delay that can be adjusted
using an external resistor to set the bias current for an
internal delay cell. The LVTTL/LVCMOS outputs feature
200ps maximum output-to-output skew and ±100ps maxi-
mum added peak-to-peak jitter.
The MAX9160 is designed to operate with a 3.3V sup-
ply voltage over the extended temperature range of
-40°C to +85°C. This device is available in 28-pin
exposed- and nonexposed-pad TSSOP and 32-lead
5mm x 5mm QFN packages.
19-2392; Rev 0; 4/02
Typical Application Circuit and Functional Diagram appear
at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations continued at end of data sheet.
Cellular Base Stations
Servers
Add/Drop Multiplexers
TOP VIEW
OUTA5
OUTA6
OUTB0
OUTB1
SE_IN
RSET
GND
GND
ENA
ENB
V
SEL
IN+
IN-
CC
________________________________________________________________ Maxim Integrated Products
10
11
12
13
14
1
2
3
4
5
6
7
8
9
14 LVTTL/LVCMOS Output Clock Driver
General Description
MAX9160
TSSOP
Pin Configurations
Digital Cross-Connects
DSLAMs
Networking Equipment
Applications
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LVDS or LVTTL/LVCMOS Input to
OUTA4
OUTA3
GND
OUTA2
OUTA1
V
OUTA0
OUTB6
GND
OUTB5
OUTB4
V
OUTB3
OUTB2
CC
CC
o LVDS or LVTTL/LVCMOS Input Selection
o LVDS Input Fail-Safe Sets Outputs High for Open,
o Two Output Banks with Separate Bank Enables
o Integrated Output Series Termination for 60Ω
o 200ps (max) Output-to-Output Skew
o ±100ps (max) Peak-to-Peak Added Output Jitter
o 42% to 58% Output Duty Cycle at 125MHz
o Guaranteed 125MHz Operating Frequency
o LVDS Input Is High Impedance with V
o 28-Pin Exposed- and Nonexposed-Pad TSSOP
o -40°C to +85°C Operating Temperature
o 3.0V to 3.6V Supply Voltage
*Future product—contact factory for availability.
**Exposed pad.
V
H = high logic level
Open
MAX9160EUI
MAX9160AEUI
MAX9160EGJ*
EN_
ID
L or
Undriven Short, or Undriven Parallel Termination
Lines
or Open (Hot Swappable)
or 32-Lead QFN Packages
H
H
H
H
H
= V
PART
IN+
open
open
open
SEL
L or
L or
L or
H
H
X
- V
IN-
SE_IN
open
L or
H
X
X
X
X
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
Ordering Information
und r i ven p ar al l el ter m i nati on
Op en, und r i ven shor t, or
L = low logic level
X = don’t care
Function Table
≥ +50mV
≤ -50mV
V
X
X
X
ID
PIN-PACKAGE
28 TSSOP
28 TSSOP-EP**
32 QFN-EP
Features
CC
= 0V
OUT_
H
H
H
L
L
L
1

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