MAX9763 Maxim Integrated Products, MAX9763 Datasheet - Page 16

• Manufacturer Part Number: MAX9763
• Description: (MAX9760 - MAX9763) Stereo 3W Audio Power Amplifiers
• Manufacturer: Maxim Integrated Products

w w w . d a t a s h e e t 4 u . c o m
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Figure 5. Early STOP Condition
Figure 6. Slave Address Byte Definition
MAX9762. The master terminates transmission by issu-
ing the STOP condition, this frees the bus. If a REPEAT-
ED START condition is generated instead of a STOP
condition, the bus remains active.
The MAX9760/MAX9762 recognize a STOP condition at
any point during the transmission except if a STOP con-
dition occurs in the same high pulse as a START condi-
tion (Figure 5). This condition is not a legal I
at least one clock pulse must separate any START and
STOP conditions.
A REPEATED START (S
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S
master is writing to several I
want to relinquish control of the bus. The MAX9760/
MAX9762 serial interface supports continuous write
operations with or without an S
them. Continuous read operations require S
because of the change in direction of data flow.
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S
SDA
SCL
SDA
SCL
A6
ILLEGAL EARLY STOP CONDITION
A5
LEGAL STOP CONDITION
START
r
STOP
may also be used when the bus
A4
REPEATED START Conditions
r
A3
) condition may indicate a
START
ILLEGAL
2
STOP
C devices and does not
Early STOP Conditions
A2
r
condition separating
A1
A0
r
2
conditions
R/W
C format,
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9760/MAX9762 generate an ACK
when receiving an address or data by pulling SDA low
during the night clock period. When transmitting data,
the MAX9760/MAX9762 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9760/
MAX9762 wait for a START condition followed by its
slave address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the master
is writing to or reading from the MAX9760/MAX9762
(R/W = 0 selects the write condition, R/W = 1 selects
the read condition). After receiving the proper address,
the MAX9760/MAX9762 issue an ACK by pulling SDA
low for one clock cycle.
The MAX9760/MAX9762 have a factory-/user-pro-
grammed address. Address bits A6–A2 are preset,
while A0 and A1 is set by ADD. Connect ADD to either
V
slave address
There are three registers that configure the
MAX9760/MAX9762: the MUTE register, SHDN register,
and control register. In write data mode (R/W = 0), the
register address and data byte follow the device
address (Figure 7).
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel, bit 4
(MUTER) controls the right channel. A logic high mutes
the respective channel, a logic low brings the channel
out of mute.
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic high
in bit 0 of the SHDN register shuts down the device; a
logic low turns on the device. A logic high is required in
bits 2 to 7 to reset all registers to their default settings.
DD
, GND, SCL, or SDA to change the last 2 bits of the
(Table
2).
Acknowledge Bit (ACK)
Write Data Format
MUTE Register
SHDN Register
Slave Address