ADS7816C Burr-Brown Corporation, ADS7816C Datasheet - Page 9

• Manufacturer Part Number: ADS7816C
• Description: 12-Bit High Speed Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

The reference current diminishes directly with both conver-
sion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the con-
verter more quickly during a given conversion period will
not reduce the overall current drain from the reference. The
reference current changes only slightly with temperature.
See the curves, “Reference Current vs Sample Rate” and
“Reference Current vs Temperature” in the Typical Perfor-
mance Curves section for more information.
DIGITAL INTERFACE
SERIAL INTERFACE
The ADS7816 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for D
the system can use the falling edge of DCLOCK to capture
each bit.
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, D
FIGURE 1. ADS7816 Basic Timing Diagrams.
CS/SHDN
CS/SHDN
DCLOCK
DCLOCK
D
D
OUT
OUT
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
t
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
DATA
OUT
t
t
HI-Z
HI-Z
SMPL
SMPL
t
t
CSD
CSD
: During this time, the bias current and the comparator power down and the reference input
t
t
SUCS
SUCS
is enabled and will output a LOW
NULL
NULL
BIT
BIT
(MSB)
(MSB)
B11
B11
B10 B9
B10 B9
B8
B8
OUT
B7
t
B7
t
CONV
CONV
t
t
CYC
CYC
is acceptable,
B6
B6
B5
B5
B4
B4
B3
B3
9
B2
B2
value for one clock period. For the next 12 DCLOCK
periods, D
nificant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B11) has been repeated, D
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
TABLE I. Timing Specifications –40 C to +85 C.
B1 B0
B1
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
SMPL
CONV
CYC
CSD
SUCS
hDO
dDO
dis
en
f
r
B0
(1)
t
B1
DATA
CS Rising to D
Analog Input Sample TIme
HI-Z
OUT
DCLOCK Falling to D
DCLOCK Falling to Next
POWER
DOWN
B2
Current D
DCLOCK Falling to
Conversion Time
Throughput Rate
DCLOCK Rising
D
DESCRIPTION
DCLOCK LOW
D
B3
CS Falling to
CS Falling to
OUT
will output the conversion result, most sig-
OUT
D
Enabled
OUT
NULL
BIT
Rise Time
B4
OUT
Fall Time
Valid
OUT
B11 B10 B9
Not Valid
B5
t
POWER DOWN
DATA
Tri-State
B6
OUT
B7
ADS7816
B8
B8
MIN
1.5
30
15
B9 B10 B11
TYP
12
85
25
50
70
60
(2)
MAX
200
150
100
100
100
2.0
50
0
HI-Z
Clk Cycles
Clk Cycles
UNITS
kHz
ns
ns
ns
ns
ns
ns
ns
ns
OUT
®