ADS7834E Burr-Brown Corporation, ADS7834E Datasheet - Page 8

• Manufacturer Part Number: ADS7834E
• Description: 12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

internal reference. This reference can be used to supply a
small amount of source current to an external load, but the
load should be static. Due to the internal 10k
dynamic load will cause variations in the reference voltage,
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage
seen at the buffer input. The amount of reduction depends on
the load and the actual value of the internal “10k ” resistor.
The value of this resistor can vary by 30%.
The V
placed as close as possible to the ADS7834 package. In
addition, a 2.2
parallel with the ceramic capacitor. Placement of this capaci-
tor, while not critical to performance, should be placed as
close to the package as possible.
EXTERNAL REFERENCE
The internal reference is connected to the V
internal buffer via a 10k series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.0V
to 2.55V, corresponding to an analog input range of 2.0V to
2.55V.
While the external reference will not source significant
current into the V
10k
reference (the exact value of the resistor will vary up to
still be bypassed to ground with at least a 0.1 F ceramic
capacitor (placed as close to the ADS7834 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2 F tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. For example, a 2.048V refer-
ence provides for a 0V to 2.048V input range—or 500nV per
LSB. The other is to provide greater stability over tempera-
ture. (The internal reference is typically 20ppm/ C which
translates into a full-scale drift of roughly 1 output code for
every 12 C. This does not take into account other sources of
full-scale drift). If greater stability over temperature is needed,
then an external reference with lower temperature drift will
be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7834. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
30% from part to part). In addition, the V
REF
resistor that is terminated into the 2.5V internal
pin should be bypassed with a 0.1 F capacitor
®
ADS7834
F tantalum capacitor should be used in
REF
pin, it does have to drive the series
REF
REF
pin and to the
pin should
resistor, a
8
FIGURE 2. Serial Data and Clock Timing.
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (T
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (t
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high-imped-
ance and goes LOW, the conversion has started and that
clock cycle is the first of the conversion.)
In addition if CONV is completely asynchronous to CLK
and CLK is continuous, then there is the possibility that
CLK will transition just prior to CONV going LOW. If this
DATA
CLK
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CONV
t
t
CKDH
CKDS
t
CKCH
CKCS
CKDE
CKDD
CKPD
CVHD
CVPU
CVDD
CVPD
t
t
t
CKSP
CVSP
ACQ
CKP
CKH
CVH
DRP
CKL
CVL
Clock Falling to Power-Down Mode
Clock Falling to Next Data Valid
CONV Changing State to DATA
CONV Setup to Clock Falling
Clock Falling to DATA Enabled
CONV Hold after Clock Falls
CONV Rising to Sample Mode
CONV Rising to Full Power-up
Clock Falling to Sample Mode
CONV Falling to Start of CLK
Clock Falling to Current Data
CONV Falling to Hold Mode
C
(for hold droop < 0.1 LSB)
CONV Changing State to
LOAD
t
Clock Falling to DATA
CKH
Bit No Longer Valid
Power-Down Mode
Conversion Time
Acquisition Time
High Impedance
(Aperture Delay)
High Impedance
DESCRIPTION
Clock Period
CONV HIGH
Clock HIGH
CONV LOW
CKCH
Clock LOW
= 30pF).
t
CKP
and t
t
CKL
CKCS
t
CKDS
(1)
(1)
). However, if these times
1.625
MIN
350
125
50
50
40
40
10
10
5
A
= –40 C to +85 C,
TYP
15
30
20
70
50
50
70
50
5
5
5
MAX
5000
100
100
50
50
5
t
CKDH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s