ADS7852YB Burr-Brown Corporation, ADS7852YB Datasheet - Page 12

• Manufacturer Part Number: ADS7852YB
• Description: 12-Bit/ 8-Channel/ Parallel Output ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

POWER-DOWN MODE
The ADS7852 has two different power-down modes: the
Nap mode and the Sleep mode. In the Nap mode, all analog
and digital circuitry, with the exception of the voltage
reference, is powered off. In the Sleep mode, everything is
powered off.
While the Sleep mode affords the lowest power consump-
tion, the time to come out of Sleep mode can be considerable
since it takes the internal reference voltage a finite amount of
time to power up and reach a stable value. This latency can
result in spurious output data for a minimum of ten conver-
sion cycles at a 500kHz sampling rate. It should also be
noted that any external load connected to the V
exacerbate this effect since a discharge path for the V
bypass capacitor is provided during the Sleep cycle. Even the
parasitic leakage of the bypass capacitor itself should be
considered if the unit is left in the Sleep mode for an
extended period. After power-up, this capacitor must be
recharged by the internal reference voltage and the on-chip
10k
bypass capacitor is completely discharged), the output data
can be invalid for several hundred milliseconds.
FIGURE 3. Entering Nap Using RD and A0.
FIGURE 4. Initiating Wake-Up Using RD and A0.
series resistor. Under worst-case conditions (e.g., the
®
ADS7852
BUSY
CLK
CLK
CS
RD
A1
A0
CS
RD
NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7852 in sample mode. A1 must be LOW to initiate wake-up.
A1
A0
NOTE: Rising edge of 1
t
11
t
13
t
14
st
RD while A0 = 1 initiates power-down immediately. A1 must be LOW to enter Nap mode.
t
11
REF
t
6
t
6
pin will
t
REF
7
t
7
12
t
8
t
8
t
Since the Nap mode maintains the voltage on the V
keeping the internal reference powered-up, valid conversions
are available immediately after the Nap mode is terminated.
The simplest way to use the power-down mode is following
a conversion. After a conversion has finished and BUSY has
returned HIGH, CS and RD must be brought LOW for a
minimum of 25ns. When RD and CS are returned HIGH, the
ADS7852 will enter the power-down mode on the rising
edge of RD. If CS is always kept LOW, the power-down
mode will be controlled exclusively by RD. Depending on
the status of the A0 and A1 address pins, the ADS7852 will
either enter the Nap mode, the Sleep mode, or be returned
to normal operation in the sampling mode. See Table II and
Figures 3 and 4 for further details.
12
TABLE II. ADS7852 Power-Down Mode.
t
RD
12
= Signifies rising edge of RD pin. X = Don't care
t
15
A2
X
X
X
X
A1
0
1
0
1
A0
0
0
1
1
POWER-DOWN MODE
Sleep
Sleep
None
Nap
REF
pin by