ADS7864YB Burr-Brown Corporation, ADS7864YB Datasheet - Page 11

• Manufacturer Part Number: ADS7864YB
• Description: 500kHz/ 12-Bit/ 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

START OF A CONVERSION
By bringing one or all of the HOLDX signals low, the input
data of the corresponding channel X is immediately placed
in the hold mode (5ns). The conversion of this channel X
follows as soon as the AD-converter is available for the
particular channel. If other channels are already in the hold
mode but not converted, then the conversion of channel X is
put in the queue until the previous conversion has been
completed. If more than one channel goes into hold mode
within one clock cycle, then channel A will be converted
first if HOLDA is one of the triggered hold signals. Next
channel B will be converted and at last channel C. If it
is important to detect a hold command during a certain
clock-cycle, then the falling edge of the hold signal has to
occur at least 10ns before the falling edge of clock. (Figure
8, t
new conversion. The hold signal has to be high for at least
15ns (Figure 8, t
has to stay low for at least 20ns (Figure 8, t
FIGURE 8. Start of the Conversion.
FIGURE 9. Timing of One Conversion Cycle.
HOLDC
CLOCK
HOLDA
HOLDB
RESET
1
). The hold signal can remain low without initiating a
t
8
t
9
t
6
2
) before it is brought low again and hold
CLOCK
HOLDB
BUSY
RD
CS
A0
t
7
t
2
t
t
3
1
t
5
3
).
11
t
t
11
10
In the example of Figure 8, the signal HOLDB goes low first
and channel B0 and B1 will be converted first. The falling
edges of HOLDA and HOLDC occur within the same clock
cycle. Therefore, the channels A0 and A1 will be converted
as soon as the channels B0 and B1 are finished (plus
acquisition time). When the A-channels are finished, the
C-channels will be converted. The second HOLDA signal is
ignored, as the A-channels are not converted at this point in
time.
Once a particular hold signal goes low, further impulses of
this hold signal are ignored until the conversion is finished
or the part is reset. When the conversion is finished (BUSY
signal goes high) the sampling switches will close and
sample the selected channel. The start of the next conversion
must be delayed to allow the input capacitor of the ADS7864
to be fully charged. This delay time depends on the driving
amplifier, but should be at least 175ns (Figure 9, t
The ADS7864 can also convert one channel continuously, as
it is shown in Figure 9 with channel B. Therefore, HOLDA
and HOLDC are kept high all the time. To gain acquisition
TIMING SPECIFICATIONS
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Successive conversion time (16 • t
Input capacitor charge time
Address setup before RD
HOLD HIGH time to be
HOLD (A, B, C) before
CS before end of RD
First hold after reset
falling edge of clock
Reset pulse width
recognized again
HOLD LOW time
Clock HIGH time
Clock LOW time
Conversion time
RD HIGH time
Clock period
DESCRIPTION
t
4
ADS7864
5
)
175
125
MIN
10
15
20
40
40
20
20
10
30
30
2
12.5 • t
TYP
5
MAX
4
).
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
®