AD1819A Analog Devices, AD1819A Datasheet - Page 19

• Manufacturer Part Number: AD1819A
• Description: ac '97 Soundport(r) Codec
• Manufacturer: Analog Devices

The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time
slot within the current audio frame. A “1” in a given bit position of Slot 0 indicates that the corresponding time slot within the cur-
rent audio frame has been assigned to a data stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the
source of the data, (AD1819A for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0s during
that slot’s active time. The AD1819A stuffs all invalid slots with zeros and ignores invalid input slots.
Additionally, for power savings, all clock, sync, and data signals can be halted.
For multiple codec operations, the AD1819A supports an enhanced mode for communicating with up to two additional codecs. The
Slave 1 AD1819A codec uses Slots 5 and 6, while Slave 2 uses Slots 7 and 8 as shown in the following diagram.
AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AD1819A’s DAC
inputs and control registers. As briefly mentioned earlier, each audio output frame supports up to twelve 20-bit outgoing data time
slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure.
Within Slot 0 the first bit is a global bit (SDATA_OUT Slot 0, Bit 15), which flags the validity for the entire audio frame. If the
“Valid Frame” bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12-bit
positions sampled by AC ’97 indicate which of the corresponding 12 time slots contain valid data. In this way input DAC data
streams of differing sample rates can be transmitted across the AC-Link at its fixed 48 kHz audio frame rate. The following diagram
illustrates the time-slot-based AC-Link protocol.
A new audio output frame begins with a low-to-high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On
the immediately following falling edge of BIT_CLK, the AD1819A samples the assertion of SYNC. This falling edge marks the time
when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC ’97 controller
transitions SDATA_OUT into the first bit position of Slot 0 (Valid Frame Bit). Each new bit position is presented to AC-Link on a
rising edge of BIT_CLK, and subsequently sampled by AD1819A on the following falling edge of BIT_CLK. This sequence ensures
that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
REV. 0
SDATA_IN
BIT_CLK
SYNC
END OF PREVIOUS
AUDIO FRAME
OUTGOING STREAMS
INCOMING STREAMS
CODEC
READY
12.2888MHz
SLOT(1) SLOT(2)
SYNC
(1) = TIME SLOT CONTAINS VALID PCM DATA
TAG PHASE
81.4ns
SLOT # ....
PHASE
TIME SLOT “VALID”
TAG
TAG
TAG
SLOT(12)
BITS
STATUS
CMD
ADR
ADR
Figure 9. Standard Bidirectional Audio Frame
1
Figure 10. AC-Link Audio Output Frame
“0”
STATUS
DATA
DATA
CMD
2
“0”
LEFT
LEFT
PCM
PCM
3
“0”
RIGHT
RIGHT
PCM
PCM
19
4
20.8 s (48kHz)
–19–
SLOT 1
LEFT
LEFT
PCM
PCM
5
SLAVE 1
ENHANCED MODE
RIGHT
0
RIGHT
PCM
PCM
DATA PHASE
6
19
LEFT
LEFT
PCM
PCM
7
SLOT 2
SLAVE 2
DATA PHASE
RIGHT
RIGHT
PCM
PCM
8
0
RSRVD
RSRVD
9
19
SLOT 3
RSRVD
RSRVD
10
0
RSRVD
RSRVD
11
RSRVD
RSRVD
AD1819A
12
19
SLOT 12
0