AD1833 Analog Devices, AD1833 Datasheet - Page 14

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AD1833

Manufacturer Part Number
AD1833
Description
Multi-Channel, 24-bit, 192 KHZ Sigma-delta DAC
Manufacturer
Analog Devices
Datasheet

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AD1833
Packed Mode 128
In Packed Mode 128, all six data channels are “packed” into
one sample interval on one data pin. The BCLK runs at 128 ×
f
val. Each sample interval is broken into eight time slots, six slots
of 20 BCLKs and two of four BCLKs. The data length is restricted
in this mode to a maximum of 20 bits. The three left channels
are written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLKs and then the three right channels are
written. The L/RCLK defines the left and right data transmis-
sion; it is high for the three left channels and low for the three
right channels.
L/RCLK
S
L/RCLK
; therefore there are 128 BCLK periods in each sample inter-
BCLK
DATA
BCLK
DATA
24-BIT DATA
20-BIT DATA
16-BIT DATA
BCLK
SLOT 1
LEFT 0
SLOT 1
LEFT 0
MSB
MSB
MSB
MSB
MSB
MSB
–1
–1
–1
SLOT 2
MSB
MSB
MSB
LEFT 1
–2
–2
–2
SLOT 2
LEFT 1
MSB
MSB
MSB
–3
–3
–3
20-BIT DATA
16-BIT DATA
MSB
MSB
MSB
–4
–4
–4
BCLK
SLOT 3
LEFT 2
SLOT 3
LEFT 2
MSB
MSB
LSB
LSB
LSB
+8
+4
BLANK SLOT
MSB
MSB
4 SCLKs
–1
–1
LSB
LSB
+7
+3
MSB
MSB
LSB
LSB
–2
–2
+6
+2
Packed Mode 256
In Packed Mode 256 all six data channels are “packed” into one
sample interval on one data pin. The BCLK runs at 256 × f
therefore there are 256 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots of 32 BCLKs
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on
the falling edge of BCLK with a one BCLK period delay from
the start of the slot. After the three left channels are written,
there is a space of 32 BCLKs and then the three right channels
are written. The L/RCLK defines the left and right data trans-
mission; it is low for the three left channels and high for the
three right channels.
MSB
MSB
LSB
LSB
–3
–3
+5
+1
RIGHT 0
SLOT 4
RIGHT 0
SLOT 4
MSB
MSB
–4
–4
LSB
LSB
+4
LSB
+3
LSB
+2
RIGHT 1
SLOT 5
RIGHT 1
SLOT 5
LSB
LSB
+4
LSB
+1
LSB
+3
LSB
LSB
+2
RIGHT 2
SLOT 6
RIGHT 2
SLOT 6
LSB
+1
LSB
BLANK SLOT
4 SCLKs
S
;

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