AD1835 Analog Devices, AD1835 Datasheet - Page 4

• Manufacturer Part Number: AD1835
• Description: 2 ADC, 8DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

AD1835–SPECIFICATIONS
TIMING
Parameter
MASTER CLOCK AND RESET
SPI PORT
DAC SERIAL PORT
ADC SERIAL PORT
Packed 256 Modes (Slave)
t
t
t
t
t
t
t
t
t
t
t
t
t
Normal Mode (Slave)
Normal Mode (Master)
Normal Mode (Slave)
Packed 256 Mode (Master)
MH
ML
PDR
CCH
CCL
CCP
CDS
CDH
CLS
CLH
COE
COD
COTS
t
t
f
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
DB
DB
AB
DBH
DBL
DLS
DLH
DDS
DDH
DBH
DBL
DLS
DLH
DDS
DDH
ABD
ALD
ABDD
ABH
ABL
ALS
ALH
PABD
PALD
PABDD
MCLK High
MCLK Low
PD/RST Low
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ABCLK Delay
ALRCLK Delay Low
ASDATA Delay
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
ABCLK Delay
LRCLK Delay
ASDATA Delay
PRELIMINARY TECHNICAL DATA
Min
15
15
20
40
40
80
10
10
10
10
60
60
64
10
10
10
10
15
15
256
10
5
10
10
60
60
64
5
15
f
f
S
S
f
S
–4–
Max
15
20
25
25
5
10
20
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
To ABCLK Rising
From ABCLK Rising
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
REV. PrA