AD1836 Analog Devices, AD1836 Datasheet - Page 3

• Manufacturer Part Number: AD1836
• Description: Multi-channel 96kHz Codec
• Manufacturer: Analog Devices

DIGITAL FILTERS at 44.1 kHz
ADC DECIMATION FILTER
DAC INTERPOLATION FILTER
TIMING
Parameter
MASTER CLOCK AND RESET
SPI PORT
DAC SERIAL PORT
REV. PrC
Packed 128, 256 Modes
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Attenuation
Group Delay
Pass Band
Pass Band Ripple
Transition Band
Stop Band
Stop Band Attenuation
Group Delay
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
Normal Modes
MH
ML
MCLK
MCLK
PDR
CCH
CCL
CCP
CDS
CDH
CLS
CLH
CODE
COD
COH
COTS
t
t
t
f
t
t
t
t
t
t
t
f
t
t
t
t
DBH
DBL
DBP
DB
DLS
DLH
DDS
DDH
DBH
DBL
DBP
DB
DLS
DLH
DDS
DDH
MCLK High
MCLK Low
MCLK Period
MCLK Freq
PD/RST Low
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Hold
COUT Three-State
DBCLK High
DBCLK Low
DBCLK Period
DBCLK Freq
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
DBCLK High
DBCLK Low
DBCLK Period
DBCLK Freq
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
Min
min
min
min
min
4500
min
min
min
min
min
min
min
min
min
min
min
max
min
min
min
min
min
min
min
min
min
min
min
–3–
Min
Max
max
max
max
max
max
max
max
max
Typ
20
± 0.0001
22
24
120
TBD
20
± 0.01
22
24
70
TBD
Unit
ns
ns
ns
ns
MCLK Periods
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Comments
256 × f
512 × f
768 × f
Reset to SPI Register Write
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
S
S
S
Unit
kHz
dB
kHz
kHz
dB
µs
kHz
dB
kHz
kHz
dB
µs
AD1836