AD1837 Analog Devices, AD1837 Datasheet - Page 12

• Manufacturer Part Number: AD1837
• Description: 2 ADC, 8DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

AD1837
RESET and Power-Down
PD/RST will power down the chip and set the control regis-
ters to their default settings. After PD/RST is deasserted, an
initialization routine will run inside the AD1837 to clear all
memories to zero. This initialization lasts for approximately
20 LRCLK intervals. During this time it is recommended that
no SPI writes occur.
Power Supply and Voltage Reference
The AD1837 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 µF should also be
provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate
supplies for the analog and digital sections. If this is not pos-
sible, it is recommended that the analog and digital supplies be
isolated by means of two ferrite beads in series with the bypass
capacitor of each supply. It is important that the analog supply
be as clean as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
MCLK
12.288MHz
CLATCH
CCLK
COUT
CIN
t
COE
t
CLS
D15
CLOCK SCALING
ADC O/P
PRELIMINARY TECHNICAL DATA
t
DAC I/P
CCP
X 2/3
D14
X 1
X 2
48/96/192kHz
Figure 2. Modulator Clocking Scheme
48/96kHz
t
COD
Figure 3. Format of SPI Timing
D9
D9
t
CCH
IMCLK = 24.576MHz
t
CDS
t
CCL
D8
D8
t
CDH
INTERPOLATION
–12–
OPTIONAL
FILTER
HPF
parallel combination of 10 µF and 100 nF. The reference volt-
age may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the V
Serial Control Port
The AD1837 has an SPI-compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
The format is similar to the Motorola SPI format except the
input data word is 16-bits wide. The maximum serial bit clock
frequency is 16 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to Right-Justified
(RJ), Left-Justified DSP (DSP), or Left-Justified (LJ). In the RJ
mode, it is necessary to set Bits 4 and 5 to define the width of
the data word.
ADC ENGINE
DECIMATOR/
DAC ENGINE
MODULATOR
FILTER
Σ-∆
REF
pin should be limited to less than 50 µA.
MODULATOR
DAC
Σ-∆
D0
D0
t
CLH
t
COTS
ANALOG
OUTPUT
ANALOG
INPUT
REV. PrA
2
S