AD1839A Analog Devices, AD1839A Datasheet - Page 4

• Manufacturer Part Number: AD1839A
• Description: 2 ADC, 6 DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

AD1839A
TIMING SPECIFICATIONS
Parameter
MASTER CLOCK AND RESET
SPI PORT
DAC SERIAL PORT (48 kHz and 96 kHz)
ADC SERIAL PORT (48 kHz and 96 kHz)
t
t
t
t
t
t
t
t
t
t
t
t
t
Normal Mode (Slave)
Packed 128/256 Modes (Slave)
Normal Mode (Master)
Normal Mode (Slave)
Packed 128/256 Mode (Master)
MH
ML
PDR
CCH
CCL
CCP
CDS
CDH
CLS
CLH
COE
COTS
COD
t
t
f
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
DB
DB
AB
DBH
DBL
DLS
DLH
DDS
DDH
DBH
DBL
DLS
DLH
DDS
DDH
ABD
ALD
ABDD
ABH
ABL
ALS
ALH
ABDD
PABD
PALD
PABDD
MCLK High
MCLK Low
PD/RST Low
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ABCLK Delay
ALRCLK Delay
ASDATA Delay
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
ASDATA Delay
ABCLK Delay
LRCLK Delay
ASDATA Delay
Min
15
15
20
40
40
80
10
10
10
10
60
60
64
10
10
10
10
15
15
256
10
10
10
10
60
60
64
5
15
f
f
S
S
f
S
–4–
Max
15
20
25
25
5
10
15
40
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
From CCLK Rising Edge
From CCLK Falling Edge
From ABCLK Falling Edge
Comments
To CCLK Rising Edge
To CCLK Rising Edge
From CCLK Rising Edge
From CLATCH Falling Edge
From CLATCH Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
To ABCLK Rising Edge
From ABCLK Rising Edge
From ABCLK Falling Edge
From MCLK Rising Edge
From ABCLK Falling Edge
REV. A