AD1845 Analog Devices, AD1845 Datasheet - Page 31

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. B
ISA BUS BCLK
ISA BUS BCLK
CDRQ /PDRQ
DBDIR OUTPUT
CDRQ /PDRQ
DBEN & DBDIR
DBEN OUTPUT
CDAK/PDAK
ISA BUS BCLK
CDRQ OUTPUT
ISA BUS BCLK
PDRQ OUTPUT
CDAK/PDAK
RD OR WR
CDAK INPUT
PDAK INPUT
Figure 22. 8-Bit Stereo or 16-Bit Mono DMA Cycle
RD OR WR
OUTPUTS
Figure 21. 8-Bit Mono DMA Write/Playback Cycle
OUTPUTS
DATA7:0
Figure 20. 8-Bit Mono DMA Read/Capture Cycle
DATA7:0
INPUTS
INPUTS
WR INPUT
OUTPUTS
RD INPUT
OUTPUTS
OUTPUTS
INPUTS
INPUTS
DATA7:0
DATA7:0
Figure 23. 16-Bit Stereo DMA Interrupt
HI
BYTE
LOW
t
DBDL
t
DSDL
SAMPLE
t
t
DKSU
DKSU
LEFT
t
BWDN
LOW BYTE
LEFT/
t
RDDV
BYTE
HIGH
t
t
DRHD
t
DRHD
WDSU
t
t
STW
STW
t
BWDN
BYTE
LOW
SAMPLE
t
t
t
RIGHT
DHD2
DKHDb
DKHDa
HIGH BYTE
RIGHT/
t
DHD1
BYTE
HIGH
–31–
DMA Interrupt
Writing to the internal 16-bit Base Count Register sets up the
count value for the number of samples to be transferred. Note
that the number of bytes transferred for a given count will be a
function of the selected global data format. The internal Cur-
rent Count Register is updated with the current contents of the
Upper and Lower Base Count Registers when a write occurs to
the Upper Base Count Register.
The Current Count Register cannot be read by the host. Read-
ing the Base Count Registers will only read back the initializa-
tion values written to them.
The Current Count Register decrements by one after every
sample transferred. An interrupt event is generated after the
Current Count Register is zero and an additional playback
sample is transferred. The INT bit in the Status Register always
reflects the current internal interrupt state defined above. The
external INT pin will only go active HI if the Interrupt Enable
(wIEN) bit in the Interface Configuration Register is set. If the
IEN bit is zero, the external INT pin will always stay LO, even
though the Status Register’s INT bit may be set.
POWER UP AND RESET
The PWRDWN and RESET pin should be held in the active
LO state when power is first applied to the AD1845. The
AD1845’s initialization commences when PWRDWN and
RESET have both been deasserted (HI). While initializing, the
AD1845 ignores all writes and all reads will yield “1000 0000
(80h).” At the conclusion of initialization, all registers will be
set to their default values as listed in Figure 5. The conclusion
of the initialization period, after approximately 512 ms, can be
detected by polling the index register for some value other than
“1000 0000 (80h).”
Upon power-up the AD1845 enters the Mode Change Enable
(MCE) state. In the default condition, the AD1845 expects to
receive a 24.576 MHz input clock source. To change the selec-
tion of the current or default input clock source, follow the steps
listed below:
• Wait for the AD1845 to initialize.
• Set the MODE2 bit to 1.
• Enter the MCE state, write to the Crystal/Clock Input Fre-
• The AD1845 will now resynchronize its internal states to the
• Clear the MCE bit.
quency Select bits (XFS2:0) to select the desired frequency.
new clock. Writes to the AD1845 will be ignored. Poll the
index register for some value other than “1000 0000 (80h).”
AD1845