AD1981BL Analog Devices, AD1981BL Datasheet - Page 19

• Manufacturer Part Number: AD1981BL
• Description: Low Voltage AC'97 Soundmax Codec
• Manufacturer: Analog Devices

All registers not shown and bits containing an X are assumed to be reserved. The Extended Audio Status and Control register is a read/write register that provides
status and control of the extended audio features.
VRA
SPDIF
SPSA[1:0]
SPCV
VFORCE
REV. 0
Reg
No. Name
2Ah Ext’d Audio Stat/Ctrl VFORCE X
Variable Rate Audio (Read/Write).
VRA = 0 sets fixed sample rate audio at 48 kHz (reset default).
VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).
SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).
SPDIF = 1 enables the SPDIF transmitter.
SPDIF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is allowed
to be set high only if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the
SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low,
indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF
transmitter is actually enabled.
SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults,
depending on the codec ID configuration.
SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the
driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent
of the SPDIF enable bit status.
SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).
SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).
Validity Force Bit (Reset Default = 0).
When asserted, this bit forces the SPDIF stream Validity flag (Bit 28 within each SPDIF L/R subframe) to be
controlled by the V bit (D15) in Register 3Ah (SPDIF control register).
VFORCE = 0 and V = 0; the Validity bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
VFORCE = 1 and V = 0; the Validity bit is forced low, indicating subframe data is valid.
VFORCE = 1 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.
D15
D14 D13
Extended Audio Status and Control Register (Index 2Ah)
X
D12
X
D11 D10
X
SPCV
–19–
D9
X
D8
X
D7
X
D6
X
D5
SPSA1 SPSA0 X
D4
D3 D2
SPDIF X
AD1981BL
D1 D0
VRA 0000h
Default