RA23P Analog Intergrations Corporation, RA23P Datasheet - Page 7

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RA23P

Manufacturer Part Number
RA23P
Description
Aic809 Aic810 3-pin Microprocessor Reset Circuits
Manufacturer
Analog Intergrations Corporation
Datasheet
RESET OUTPUT
μP will be activated at a valid reset state. These
μP supervisory circuits assert reset to prevent
code
power-down, or brownout conditions.
V
threshold, an internal timer keeps RESET low
for the reset timeout period; after this interval,
If a brownout condition occurs (VCC drops below
the reset threshold), RESET goes low. Any time
VCC goes below the reset threshold, the internal
timer resets to zero, and RESET goes low. The
NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the μP during
power-up, power-down, and brownout conditions,
AIC809
short-duration negative-going VCC transient.
ENSURING A VALID RESET OUTPUT DOWN
TO VCC=0
When VCC falls below 0.9V, AIC809 RESET
output no longer sinks current; it becomes an
open circuit. In this case, high-impedance CMOS
logic inputs connecting to RESET can drift to
undetermined voltages. Therefore, AIC809/810
with CMOS is perfect for most applications of VCC
PIN DESCRIPTIONS
GND Pin
RESET Pin (AIC810)
Vcc Pin
DETAIL DESCRIPTIONS OF TECHNICAL TERMS
RESET is guaranteed to be a logic low for
RESET goes high.
APPLICATION INFORMATION
RESET Pin (AIC809) : Active low output pin. RESET Output remains low while Vcc is below the reset
TH
>VCC>0.9V. Once VCC exceeds the reset
execution
series
are
errors
: Ground.
: Active high output pin. RESET output remains high while Vcc is below the reset
: Supply voltage.
relatively
threshold.
threshold.
during
resistant
power-up,
to
internal timer is activated after VCC returns
above the reset threshold, and RESET remains
low for the reset timeout period.
BENEFITS OF HIGHLY ACCURATE RESET
THRESHOLD
AIC809/810 with specified voltage as 5V±10% or
3V±10% are ideal for systems using a 5V±5% or
3V±5% power supply. The reset is guaranteed to
assert after the power supply falls out of regulation,
but before power drops below the minimum
specified operating voltage range of the system
ICs. The pre-trimmed thresholds are reducing the
range over which an undesirable reset may occur.
below 0.9V. However in applications where
pull-down resistor to RESET causes any leakage
currents to flow to ground, holding RESET low.
INTERFACING TO
RESET PINS
The RESET output on the AIC809N is open drain,
this device interfaces easily with μPs that have
bidirectional reset pins. Connecting the μ P
supervisor’s RESET
microcontroller’s RESET pin with a single pull-up
resistor allows either device to assert reset.
RESET must be valid down to 0V, adding a
μ
AIC809/AIC810
P WITH BIDIRECTIONAL
output directly to the
7

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